COP Memory Device With Bottom I/O Pads
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Solution Overview
Problem
The size reduction of vertical memory devices is limited due to the challenge of electrically connecting peripheral circuits to external devices, as existing technologies struggle to efficiently interface memory cell arrays with external devices.
Innovation Solution
A memory device with a cell over periphery (COP) structure is implemented, where the peripheral circuit is formed on a semiconductor substrate, and the memory cell array is stacked on top, with input-output pads overlapping the memory cell array in the vertical direction, and through-substrate vias connecting these pads to lower wiring patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a vertical memory device structure is adopted to increase integration density, then storage capacity is improved, but size reduction is limited due to interface connectivity requirements
Solution Approach 1:
The patent transitions from a planar layout where I/O pads are positioned at the periphery to a three-dimensional configuration where I/O pads are located on the bottom surface of the substrate and extend vertically through the device. This dimensional change allows the memory cell array to be positioned directly over the peripheral circuit, maximizing substrate utilization and reducing the device footprint while maintaining all necessary interface connectivity functions.
2Ease of operation
If input-output pads are positioned at the periphery for external connection, then interface functionality is achieved, but substrate area is wasted
Solution Approach 1:
The patent implements a nested configuration where the memory cell array is positioned directly over the peripheral circuit, and the input-output pads are positioned on the bottom surface extending through the substrate. This nesting allows multiple functional layers to occupy the same horizontal footprint, eliminating wasted substrate area while maintaining all interface functionality through the vertical via structure.
3Reliability
If through-substrate vias are used to connect I/O pads with lower wiring, then electrical connectivity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent incorporates the formation of through-substrate vias as an integral part of the peripheral circuit fabrication process, establishing the vertical connectivity pathways before the memory cell array is fully constructed. This preliminary action ensures that the electrical connectivity infrastructure is in place early, simplifying subsequent manufacturing steps and improving overall process reliability.
Data Source
AI summary
A memory device includes a semiconductor substrate, a peripheral circuit formed on a top surface of the semiconductor substrate, a lower insulation layer covering the peripheral circuit, a base layer formed on the lower insulation layer, a memory cell array formed on the base layer, an upper insulation layer covering the memory cell array and a plurality of input-output pads formed on a bottom surface of the semiconductor substrate. At least one of the input-output pads is disposed to be overlapped with a portion of the memory cell array in a vertical direction. The sizes of the memory device and the memory package including the memory device may be reduced through the COP structure and efficient arrangement of the input-output pads.