Cell-Over-Periphery Non-Volatile Memory Vertical Stacking
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Solution Overview
Problem
Contemporary memory devices face challenges in achieving high integration density with uncomplicated layouts and wiring designs while minimizing their footprint, which is essential for reducing the overall size and enhancing user friendliness in electronic devices.
Innovation Solution
The implementation of a Cell-Over-Periphery (COP) structured non-volatile memory device, where memory groups are vertically stacked on a semiconductor layer with peripheral circuits underneath, allowing for efficient use of space and simplified wiring by arranging word lines and bit lines in specific horizontal directions to minimize lateral area occupation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory devices use traditional layout structures with peripheral circuits arranged around memory cells, then the device provides sufficient space for circuit operations, but the overall footprint area increases and integration density decreases
Solution Approach 1:
The patent implements a three-dimensional stacked architecture where memory cell groups are vertically stacked above peripheral circuit regions. This vertical stacking approach transitions from a two-dimensional planar layout to a three-dimensional structure, allowing memory cells to occupy the vertical dimension while peripheral circuits occupy the horizontal plane, thereby increasing integration density without expanding the footprint area.
Solution Approach 2:
The patent positions peripheral circuits in the second semiconductor layer beneath corresponding memory cell groups in the first semiconductor layer. This nested arrangement allows the peripheral circuits to be embedded within the vertical profile of the memory device, with memory cells stacked directly above them, effectively nesting the peripheral circuits within the overall device structure to minimize footprint while maximizing integration density.
2Quantity of substance
If memory devices increase integration density through complex layouts, then more memory cells fit in the same area, but the layout and wiring design complexity increases
Solution Approach 1:
The patent divides the memory device into distinct functional regions: peripheral circuit regions containing driving circuits in the second semiconductor layer, and memory cell groups in the first semiconductor layer. Each region is independently designed and optimized, with standardized interconnection patterns between layers. This segmentation allows for modular design and simplifies wiring by creating regular, predictable connection patterns between corresponding regions across layers.
Solution Approach 2:
The patent employs universal interconnection patterns where bit lines and word lines extend in standardized directions (first bit lines extending in a first horizontal direction, second bit lines extending in a second horizontal direction) to connect memory cells to peripheral circuits. These standardized routing patterns can be replicated across multiple memory cell groups, reducing design complexity and enabling scalable integration while maintaining consistent wiring practices throughout the device.
Data Source
AI summary
A non-volatile memory includes a first semiconductor layer vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group and a fourth memory group. The second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively underlying the first memory group, second memory group, third memory group and fourth memory group. The first region includes one driving circuit connected to memory cells of one of the second memory group, third memory group and fourth memory group through a first word line, and another driving circuit connected to memory cells of the first memory group through a first bit line, wherein the first word line and first bit line extend in the same horizontal direction.