Solid-State Devices TRIZ Cases

An enlarged air cavity reduces ghost images caused by light multi-reflection, while an integrated cover simplifies manufacturing.

A non-volatile memory device uses an oxide-nitride-oxide structure and spacer to separate gate electrodes.

A deep trench field insulation layer with height exceeding width reduces on-resistance in power integrated devices.

Reflection-based fill patterns balance mechanical stress and preserve layout symmetry, preventing performance degradation caused by asymmetric fill procedures.

Replacing blade sawing with laser cutting increases productivity and reduces equipment costs for LED packages.

Polycrystalline silicon diodes switch resistivity states to create erasable memory cells, reducing fabrication complexity compared to floating gate structures.

Simultaneous via and trench etching creates optimized aspect ratios, reducing cross-talk while minimizing manufacturing complexity.

Inkjet dispensing selectively deposits zinc oxide seed layers, resolving material waste and patterning complexity in semiconductor manufacturing.

A data write circuit for resistive memory elements uses a complementary cell to detect writing completion and terminate current flow.

ChDT derivatives improve charge transport and external quantum efficiency while maintaining spectral characteristics.

A switch circuit uses a parasitic gate capacitor to store image data voltage on the control terminal of a second switch during sample operations.

Silane-modified polymer dispersions resolve optical defects and delamination in flexible plastic OLED displays.

A thin film transistor structure uses stacked polysilicon and amorphous silicon layers to form distinct device characteristics within a single manufacturing process.

Highly doped silicon sidewalls suppress radiation-induced charge accumulation and parasitic leakage in FinFET isolation regions.

A lamination device manufacturing method uses a reinforced wafer with an annular outer portion to join wafers and form electrodes.

Segmented composite free layers lower switching voltage while maintaining thermal stability via sequential layer switching.

A display device routes signal lines in different directions to separate power supply paths on a substrate.

Auxiliary electrode layer on spacer boosts cathode conductivity while main spacer absorbs pressure to prevent structural damage.

Silicon oxide lines vertical channel members to supply oxygen, reducing current leakage and improving thermal stability for non-silicon-based materials.

Relocating bonding regions to a concave lateral surface protects fragile silver glue electrodes from assembly damage while enabling ultra-narrow frame designs.

Surface projections on transparent substrates minimize total internal reflection to resolve limited light extraction efficiency in flip chip LEDs.

Insulating isolation layer between stacked word lines reduces leakage current and prevents data disturbance while maintaining high breakdown voltage.

Saturation control of magnetoelectric converters generates binary signals, reducing component count while increasing measurement resolution.

Segmented pixel-defining layer inlets provide fixed reference points for inkjet heads, eliminating stains from varying sub-pixel pitches.

A thin oxide layer forms on a metal separation layer via nitrogen and oxygen plasma treatment to enable substrate release.

Group pixel structures cluster same-color elements to increase aperture ratio and simplify mask deposition.

Segmented cathode electrodes with protrusions create a cavity region that absorbs bending stress, preventing cracking and peeling in flexible displays.

A cell-over-periphery non-volatile memory device stacks memory groups vertically above peripheral circuit regions to optimize space utilization.

A manganese-activated fluoride phosphor with a specific infrared absorption spectrum maintains high emission intensity through silane-based surface treatment.

Vertical stacking of LED chips via conductive adhesive layers increases effective luminous area while reducing mounting complexity.

A silicon seed layer enables low-temperature crystallization of p+ silicon germanium material, reducing interfacial defects in resistive switching devices.

Sequential solvent evaporation via boiling point differentiation resolves concurrent drying defects and improves thin film uniformity.

Cylindrical rollers in a pinching device align chip devices to wires, reducing friction and wear during high-speed manufacturing.

Bonding a reinforcing substrate prevents bending during grinding, enabling reliable electrode connection without high-temperature removal.

Laser-formed internal deteriorated layers enable clean wafer division without rear surface chipping or dust contamination.

A reflective lens directs light from an LED chip using a curved surface to minimize thickness and material usage.

A spacer structure separates adjacent carrier injection layer portions in a micro OLED display substrate to maintain electrical isolation between sub-pixels.

Recessed dielectric sidewalls eliminate edge concentration to prevent crystallization and reduce set/reset failures in resistive random access memory cells.

Applies deck-specific voltage levels during erase operations to mitigate channel voltage differences and ensure uniform programming characteristics.

A dummy die structure stabilizes redistribution chip package encapsulation layers during semiconductor processing.

A non-volatile memory channel uses distinct crystal grain sizes to enhance carrier trap density and Gate Induced Drain Leak current.

A plasma etching method using linear saturated fluorohydrocarbon compounds to selectively remove silicon-containing films.

Positioning the green subpixel closer to the pixel center balances relative luminosity distribution across the display structure.

A cup-shaped conductive member confines current flow through a phase change material plug to reduce reset energy requirements.

Symmetrical spacer distribution in the transparent area prevents film layer damage and reduces visual color errors caused by asymmetrical mask support.

A resistive memory device uses spaced lower electrode nodes and dual contact plugs to control resistance states for multi-level cell data storage.

A semiconductor process uses a polymer layer with varying thickness to protect barrier layers on gate corners from damage during etching.

Bank covers recess edge in organic light-emitting element to prevent electrical field concentration and local current flow.

Single patterning creates metal-based capacitor electrodes with superior conductivity, resolving poor performance from ion-doped semiconductors.