Symmetric Fill Pattern Generation for IC Layouts
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Solution Overview
Problem
The relentless scaling of transistors and wires in advanced semiconductor technologies leads to severe design challenges, including short-channel effects and increased wire/contact resistances, which are exacerbated by the introduction of buried power rails that cause mechanical stress and performance degradation in IC devices due to asymmetries introduced by existing fill procedures.
Innovation Solution
The proposed solution involves generating computer-implemented methods to provide symmetric fill patterns for IC devices by detecting functional components, applying reflection transformations, and merging structures to create mirror-image fill patterns across symmetry axes, thereby minimizing mechanical and electrical impacts on active devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If asymmetric fill procedures are used to fill layout spaces, then manufacturing completeness is improved, but mechanical stress and performance degradation increase due to asymmetries
Solution Approach 1:
The patent applies asymmetry principle in reverse by intentionally creating symmetric fill patterns. The system detects symmetry axes in the layout and generates fill patterns that are symmetric with respect to these axes, thereby eliminating the harmful asymmetries caused by conventional asymmetric fill procedures. This symmetric arrangement balances mechanical stress distribution and reduces performance degradation in differential circuits.
Solution Approach 2:
The patent uses counterweight principle by placing fill structures symmetrically on both sides of symmetry axes. The fill patterns in first and second sections are designed to balance each other, creating a counterbalancing effect that neutralizes mechanical stress and electrical asymmetries. This ensures that no single region dominates the stress distribution, improving overall device reliability.
2Device complexity
If conventional fill patterns are applied without considering symmetry, then fabrication simplicity is improved, but mechanical stress distribution becomes uneven causing performance degradation
Solution Approach 1:
The patent applies preliminary action by detecting symmetry axes and planning fill patterns before actual fill structure creation. The system identifies symmetry characteristics in advance, divides the layout into sections based on these symmetries, and pre-determines the symmetric arrangement of fill structures. This preliminary planning ensures balanced stress distribution from the outset without requiring complex post-processing adjustments.
Solution Approach 2:
The patent uses segmentation by dividing the layout into multiple sections based on detected symmetry axes. Each section is filled independently with fill patterns that respect the overall symmetry. This segmentation approach simplifies the fill generation process by breaking it down into manageable sections while ensuring that the combined result achieves balanced mechanical stress distribution across the entire layout.
3Reliability
If symmetric fill patterns are generated by detecting functional components and applying reflection transformations, then layout symmetry is preserved reducing mechanical stress, but computational processing time increases
Solution Approach 1:
The patent uses copying principle by creating mirror-image fill patterns through reflection transformations. Once fill structures are generated in one section, their symmetric counterparts are created by copying and reflecting them across the detected symmetry axes. This copying approach ensures layout symmetry preservation while reducing computational effort compared to generating entirely new patterns for each section.
Solution Approach 2:
The patent applies inversion principle by using reflection transformations to generate fill patterns. Instead of directly designing symmetric patterns, the system takes fill structures from one side and creates their mirror images on the other side of the symmetry axis. This inversion approach efficiently preserves layout symmetry while minimizing computational processing time.
Data Source
AI summary
Methods for providing fill patterns for IC devices are disclosed. An example method includes detecting a first device and a second device in an image, e.g., a two- or three-dimensional image representing the IC device. A line is defined based on the devices. The line divides the image into a first section and a second section. A first structure is generated based on the first device. A second structure is generated based on the second device. The second structure is a mirror image of the first structure across the line. A first fill pattern is generated in the first section based on the first structure. A second fill pattern is generated in the second section based on the first fill pattern, e.g., through a reflection transformation of the first fill pattern across the line. The two fill patterns represent patterns of fill structures to be included in the IC device.