NAND Flash Memory Erase De-biasing for Threshold Voltage Uniformity
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Solution Overview
Problem
The operation of stacked memory arrays in NAND flash memory devices presents challenges due to differences in channel voltage levels across multiple decks of memory cells, leading to variations in threshold voltages and programming characteristics during erase operations.
Innovation Solution
Implementing erase de-biasing by adjusting the voltages applied to the access lines of memory cells across different decks to mitigate channel voltage level differences, ensuring uniform erase conditions across the memory string.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If stacked memory arrays are used to increase memory density, then memory capacity is improved, but channel voltage level differences across decks cause threshold voltage variations
Solution Approach 1:
The patent applies different voltage levels to control gates of memory cells in different decks based on their position in the stack. Specifically, control gates in decks experiencing lower channel voltage levels receive higher control gate voltages, while control gates in decks experiencing higher channel voltage levels receive lower control gate voltages. This localized adjustment compensates for the voltage drops across the stacked structure and achieves uniform threshold voltage across all decks.
Solution Approach 2:
The patent changes the control gate voltage parameter dynamically based on the deck position and expected channel voltage level. By adjusting the control gate voltage magnitude for different decks, the system compensates for the inherent voltage level differences in stacked memory arrays, ensuring consistent erase and program operations across all memory cells regardless of their vertical position.
2Ease of operation
If uniform voltage levels are applied to all decks, then operation is simplified, but programming uniformity deteriorates due to channel voltage level differences
Solution Approach 1:
Instead of applying a uniform voltage to all control gates, the patent implements deck-specific voltage levels. The control circuit is configured to apply different control gate voltages to different decks based on their position in the stack and the expected channel voltage level in each deck. This localized approach maintains programming uniformity while the control circuit automates the complexity of voltage management.
Data Source
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AI summary
Methods of operating a memory include developing first and second voltage levels in first and second semiconductor materials, respectively, forming channel regions for first and second groupings of memory cells, respectively, of a string of series-connected memory cells during an erase operation while applying a third voltage level to control gates of the first grouping of memory cells and applying a fourth voltage level to control gates of the second grouping of memory cells. Apparatus include different groupings of memory cells of a string of series-connected memory cells adjacent respective portions of semiconductor material having a first conductivity type and separated from adjacent portions of semiconductor material having the first conductivity type by portions of semiconductor material having a second conductivity type, and a controller configured to apply respective and different voltage levels to control gates of memory cells of respective different groupings of memory cells during an erase operation.