Semiconductor Barrier Layer Protection via Polymer Thickness Gradient

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Solution Overview

Problem

In semiconductor processes, the barrier layer on top corners of conductive patterns is damaged during etching, leading to potential electrical shorts between gates and bit lines due to rounding or exposure of the gates.

Innovation Solution

A semiconductor process involving the formation of polymer layers with different thicknesses in an etching apparatus, where the first polymer layer is thicker on top corners than the second on bottom portions, protects the barrier layer from damage during etching by using a plasma etching process with fluorine-containing gases, ensuring the barrier layer remains intact.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If an etching process is used to remove the barrier layer on the bottom portions of openings, then the contact plugs can be formed to electrically connect with the bit lines, but the barrier layer on the top corners of the gates is simultaneously removed causing rounding or exposure of the gates

Engineering Contradiction:

Improveprecision of barrier layer removalVSAvoidintegrity of barrier layer on gate top corners

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies local quality by forming a protective polymer layer with non-uniform thickness distribution, where the layer is thicker at the top corners of the gates and thinner at the bottom portions of the openings. This localized variation in protective layer thickness enables selective protection: the thicker region protects the gate top corners from etching damage while the thinner region allows complete barrier layer removal at the opening bottoms for proper contact plug formation.

Inventive Principle:

Principle #3Local quality

2Productivity

If the barrier layer on top corners of gates is removed by the etching process, then the etching process can access the bottom portions of openings, but electrical shorts may occur between the contact plugs and the gates

Engineering Contradiction:

Improveefficiency of barrier layer removalVSAvoidelectrical insulation between gates and contact plugs

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent introduces a protective polymer layer as an intermediary substance during the etching process. This polymer layer acts as a mediator that selectively protects certain regions (gate top corners) from the etching process while allowing the etching to proceed in other regions (opening bottom portions). The polymer layer is deposited conformally and then anisotropically removed to create the desired thickness distribution, enabling the etching process to occur without causing electrical shorts.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The process effectively prevents the barrier layer on top corners from being damaged, maintaining its integrity and providing superior insulation, thus preventing electrical shorts and enhancing semiconductor device characteristics without requiring additional equipment or significantly increasing costs.

Implementation Method 1

An etching process is performed to remove the second polymer layer and the barrier layer which are disposed on the bottom portions of the first openings

Methodology Applied

Scientific EffectPlasma etching: Plasma

Implementation Method 2

using a plasma etching process with fluorine-containing gases

Methodology Applied

Scientific EffectFluorine-containing plasma: Plasma

Implementation Method 3

A first polymer layer and a second polymer layer are formed on the barrier layer

Methodology Applied

Scientific EffectPolymer deposition: Deposition (physical)

Data Source

PatentUS8309459B1Semiconductor process

Publication Date: 2012.11.13 NAN YA TECH

AI summary

A semiconductor process is provided. A substrate is provided in an etching apparatus, wherein first conductive patterns, a barrier layer and a patterned insulating layer are formed thereon. The first openings are formed between the first conductive patterns, the barrier layer covers surfaces of the first conductive patterns and the first openings, and the patterned insulating layer is formed on the first conductive patterns and has a plurality of second openings. The second openings expose the barrier layer on top corners of the first conductive patterns. Polymer layers are formed on the barrier layer, wherein a thickness of the polymer layer on the top corners of the first conductive pattern is larger than a thickness of the polymer layer on bottom portions of the first openings. An etching process is performed to remove the polymer layer and the barrier layer disposed on the bottom portions of the first openings.