Switch Circuit Parasitic Gate Capacitor Memory Pixel Element
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Solution Overview
Problem
In display devices, the layout area of memory in memory-in-pixel (MIP) systems reduces the transparent or transmissive area, leading to an unacceptably small aperture ratio when high resolution is required, due to the inverse relationship between aperture ratio and resolution.
Innovation Solution
A switch circuit with a parasitic gate capacitor is used as a sampling and memory element, allowing image data to be stored and maintained during refresh operations, reducing the need for additional memory and circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a memory is added to maintain gray level in MIP, then power consumption is reduced, but the layout area increases and aperture ratio decreases
Solution Approach 1:
The patent combines the memory function with the pixel electrode structure by forming a capacitor between the pixel electrode and a conductive layer in the common electrode region. This integration allows the memory function to be embedded within the existing pixel structure without requiring separate memory layout area, thus reducing power consumption while maintaining aperture ratio.
Solution Approach 2:
The pixel electrode structure is designed to serve multiple functions: it acts as both the display electrode and the memory storage element. By forming a capacitor using the pixel electrode and the common electrode region, the structure simultaneously performs display and data retention functions, eliminating the need for additional dedicated memory components.
2Loss of energy
If a memory is added to maintain gray level in MIP, then power consumption is reduced, but the aperture ratio decreases
Solution Approach 1:
The memory function is merged into the common electrode region rather than adding separate memory structures. The capacitor is formed between the pixel electrode and the conductive layer in the common electrode region, allowing the memory function to be embedded without occupying additional transmissive area, thus maintaining high aperture ratio while reducing power consumption.
3Device complexity
If circuit elements are reduced in DRAM type MIP, then circuit complexity is reduced and aperture ratio increases, but memory functionality must be maintained
Solution Approach 1:
The memory function is combined with the pixel electrode and common electrode structure, eliminating the need for separate memory circuit elements. The capacitor formed between these electrodes provides the necessary memory functionality for gray level maintenance while keeping the circuit simple and aperture ratio high.
Solution Approach 2:
The pixel electrode and common electrode structure serve themselves by forming the memory capacitor. The existing conductive layers and electrode structures are utilized to create the storage capacitor, eliminating the need for additional dedicated memory components and reducing circuit complexity while maintaining reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high aperture ratio and high resolution in display devices by utilizing the parasitic gate capacitor for data storage, minimizing extra memory layout and circuit elements, thus enhancing the transmissive area.
Implementation Method 1
a parasitic gate capacitor Cg is formed between the control terminal 212g and the source line Dx
Implementation Method 2
the stored image data in the second switch 212 is maintained by the parasitic gate capacitor from the sample operation to a refresh operation
Data Source
AI summary
A switch circuit, a pixel element and a display panel are provided. The switch circuit is for the pixel element, and includes switches. A switch is turned on to perform a sample operation on the pixel element. Another switch has a control terminal coupled to an image data storage capacitor of the pixel element via the switch, a data terminal to a corresponding source line, and another data terminal to the image data storage capacitor. During the sample operation, the second switch stores an image data of the image data storage capacitor in a parasitic gate capacitor existing on its control terminal. The parasitic gate capacitor maintains its stored data from the sample operation to a refresh operation in which the pixel element is refreshed. The second switch selectively electrically connects its two data terminals with each other according to stored image data in the parasitic gate capacitor.