Non-Volatile Memory Channel Grain Size Optimization
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Solution Overview
Problem
In three-dimensional NAND memory cell arrays, the existing data erasing processes are inefficient, particularly as memory capacity increases, due to limitations in the supply of holes to the channel body for effective charge cancellation across multiple memory cells.
Innovation Solution
The non-volatile memory device incorporates a semiconductor layer with distinct crystal grain sizes in its channel body, where a larger crystal grain size in the first portion opposes the word lines and a smaller size in the second portion adjacent to the selection gate, enhancing the density of crystal grain boundaries and carrier traps, thereby increasing the Gate Induced Drain Leak current for faster and more reliable data erasure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If data erasing is performed collectively by memory cell block in existing three-dimensional NAND memory, then the erasing process can be simplified, but the data erasing characteristics deteriorate as memory capacity is increased
Solution Approach 1:
The patent applies local quality by creating two distinct semiconductor layers with different crystal grain sizes in specific locations within the channel body. The first semiconductor layer with larger crystal grains is positioned in the first region, while the second semiconductor layer with smaller crystal grains is positioned in the second region. This spatial differentiation of material properties enables localized optimization of hole supply characteristics without complicating the overall erasing process structure.
Solution Approach 2:
The patent changes the physical parameter of crystal grain size in the semiconductor layers to improve hole supply characteristics. By controlling the crystal grain size parameter - larger in the first region and smaller in the second region - the patent optimizes the balance between maintaining memory cell performance and enhancing data erasing characteristics, thereby improving erasing reliability as memory capacity increases.
2Quantity of substance
If memory capacity is increased in three-dimensional NAND memory, then storage capability is improved, but data erasing efficiency deteriorates
Solution Approach 1:
The patent uses local quality by positioning semiconductor layers with different crystal grain sizes in specific regions of the channel body. The second semiconductor layer with smaller crystal grains is located in the second region where it provides enhanced hole supply characteristics, enabling efficient data erasing even in high-capacity memory structures with increased numbers of memory cells and word lines.
Solution Approach 2:
The patent changes the crystal grain size parameter of the semiconductor layers to optimize data erasing efficiency. The controlled variation in crystal grain size - with the second layer having smaller grains - increases carrier trap density and hole supply capability, maintaining high erasing efficiency despite the increased memory capacity and associated challenges in charge cancellation across multiple memory cells.
3Reliability
If crystal grain size is increased in the semiconductor layer, then memory cell performance is maintained, but the density of crystal grain boundaries and carrier traps decreases
Solution Approach 1:
The patent applies local quality by creating spatial variation in crystal grain size across different regions of the channel body. The first semiconductor layer with larger crystal grains is positioned in the first region to maintain memory cell performance, while the second semiconductor layer with smaller crystal grains is positioned in the second region to increase carrier trap density and enhance hole supply for data erasing operations.
Solution Approach 2:
The patent segments the channel body into two distinct regions with different semiconductor layer characteristics. This segmentation allows each region to be optimized for its specific function - the first region for maintaining memory cell performance and the second region for enhancing data erasing capability through increased carrier trap density - without compromising either function.
4Quantity of substance
If crystal grain size is decreased in the semiconductor layer, then the density of crystal grain boundaries and carrier traps is increased, but memory cell performance degrades
Solution Approach 1:
The patent applies local quality by positioning the second semiconductor layer with smaller crystal grains specifically in the second region, where the increased carrier trap density is beneficial for hole supply during erasing operations. The first semiconductor layer with larger crystal grains remains in the first region to maintain memory cell performance, thus avoiding the performance degradation that would occur if the entire channel body used small crystal grains.
Solution Approach 2:
The patent segments the channel body structure to isolate the effects of different crystal grain sizes to specific regions. The second semiconductor layer with smaller grains is segmented into the second region where it provides enhanced carrier trap density without affecting the memory cell performance maintained by the first semiconductor layer in the first region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces data erase time and improves erasing characteristics by increasing the supply of holes to the channel body, ensuring reliable data erasure across the memory block without degrading memory cell performance.
Implementation Method 1
enhancing the density of crystal grain boundaries and carrier traps, thereby increasing the Gate Induced Drain Leak current for faster and more reliable data erasure
Data Source
AI summary
According to an embodiment, a non-volatile memory device includes first electrodes arranged in a first direction, a second electrode disposed on a side of the first electrodes in the first direction, a semiconductor layer extending in the first direction through the first electrodes and the second electrode, and a memory film provided between the semiconductor layer and each of the first electrodes. The semiconductor layer includes crystal grains and has a first portion and a second portion, the first portion being adjacent to the first electrodes, and the second portion being adjacent to at least a part of the second electrode, wherein the first portion includes a larger crystal grain than a crystal grain in the second portion.