Non-volatile Memory Gate Electrode Spacing Reduction
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Solution Overview
Problem
Current non-volatile memory devices face challenges in achieving high integration and density due to complex fabrication processes and the need for larger, lower-cost memory solutions, particularly in reducing the distance between control and selecting gate electrodes to enhance memory cell integrity and density.
Innovation Solution
The implementation of an oxide-nitride-oxide (ONO) structure and a spacer structure to separate the control gate electrode and the selecting gate electrode, with the distance between them being smaller than or equal to the sum of the ONO structure and spacer structure widths, allowing for reduced spacing and increased memory cell density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory structure design is used, then fabrication process is simpler, but memory cell density is lower
Solution Approach 1:
The gate structure is segmented into control gate electrode and selecting gate electrode as separate components, allowing independent optimization of each gate's function and position. This segmentation enables reduced spacing between gates while maintaining proper electrical isolation through the ONO structure and spacer, thereby increasing memory cell density without compromising fabrication feasibility
Solution Approach 2:
The patent introduces a vertical stacking dimension by placing the ONO structure and spacer between the control gate and selecting gate in the vertical direction rather than only lateral separation. This dimensional change allows reduced lateral distance between gates while maintaining electrical isolation, enabling higher density memory cell design
2Area of moving object
If distance between control gate electrode and selecting gate electrode is reduced, then memory cell area is reduced, but electrical isolation between gates becomes more difficult
Solution Approach 1:
The ONO structure and spacer are introduced as intermediary elements positioned between the control gate electrode and selecting gate electrode. These intermediaries provide electrical isolation and prevent unwanted coupling between the gates, allowing the gates to be placed closer together laterally while maintaining proper electrical separation, thus reducing memory cell area without compromising reliability
Solution Approach 2:
The patent uses a composite structure consisting of the ONO multilayer (oxide-nitride-oxide) combined with a spacer material to achieve both electrical isolation and mechanical support functions. This composite approach allows effective electrical separation between gates at reduced distances, enabling smaller memory cell area while maintaining gate isolation reliability
Data Source
AI summary
A non-volatile memory device includes a semiconductor substrate, a control gate electrode, a first oxide-nitride-oxide (ONO) structure, a selecting gate electrode, a second ONO structure, and a spacer structure. The control gate electrode and the selecting gate electrode are disposed on the semiconductor substrate. The first ONO structure is disposed between the control gate electrode and the semiconductor substrate. The second ONO structure is disposed between the control gate electrode and the selecting gate electrode in a first direction. The spacer structure is disposed between the control gate electrode and the second ONO structure in the first direction. A distance between the control gate electrode and the selecting gate electrode in the first direction is smaller than or equal to a sum of a width of the second ONO structure and a width of the spacer structure in the first direction.