Coplanar Bonding Pads and Interconnections for Semiconductor Stacking
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Solution Overview
Problem
Current semiconductor devices face challenges in efficiently connecting bonding pads and interconnections across stacked semiconductor chips, leading to complexities in bonding interfaces and potential misalignment issues, which affect the reliability and versatility of semiconductor bonding.
Innovation Solution
The semiconductor device design includes a first and second semiconductor chip with bonding layers that feature bonding pads and interconnections, where the bonding pads are connected through internal vias and interconnections, allowing for coplanar surfaces and various bonding patterns, reducing the risk of misalignment and enhancing bonding reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bonding pads and interconnections are connected through multiple layers using redistribution layers, then electrical connection between chips is achieved, but the number of interconnection layers increases and misalignment issues occur
Solution Approach 1:
The bonding pad and interconnection are merged into a single coplanar structure on the same bonding layer, eliminating the need for separate redistribution layers. This integration reduces the number of interconnection layers while maintaining reliable electrical connection between stacked chips.
Solution Approach 2:
The design transitions from a multi-layer vertical interconnection approach to a coplanar arrangement where bonding pads and interconnections exist on the same layer. This dimensional reorganization simplifies the bonding interface and reduces alignment complexity.
2Manufacturing precision
If bonding pads and interconnections are arranged in different layers, then electrical connection is established, but misalignment risk increases and bonding precision is reduced
Solution Approach 1:
By merging bonding pads and interconnections into the same coplanar bonding layer, the design eliminates inter-layer alignment requirements. This single-plane arrangement significantly improves bonding alignment precision while maintaining electrical connection reliability.
3Ease of manufacture
If multiple interconnection layers are used to connect bonding pads, then electrical connection is achieved, but the number of manufacturing steps and device complexity increase
Solution Approach 1:
The integration of bonding pads and interconnections into a single coplanar structure reduces the number of manufacturing steps required. This approach simplifies the bonding process by eliminating the need to form and align multiple separate interconnection layers.
Solution Approach 2:
The design extracts and eliminates the redundant redistribution layer from the traditional multi-layer interconnection structure. This removal of unnecessary layers simplifies both the device structure and the manufacturing process.
Data Source
AI summary
A semiconductor device includes a first semiconductor chip having a first bonding layer and a second semiconductor chip stacked on the first semiconductor chip and having a second bonding layer. The first bonding layer includes a first bonding pad, a plurality of first internal vias, and a first interconnection connecting the first bonding pad and the plurality of first internal vias. The second bonding layer includes a second bonding pad bonded to the first bonding pad. An upper surface of the first interconnection and an upper surface of the first bonding pad are coplanar with an upper surface of the first bonding layer. The first interconnection is electrically connected to the plurality of different first internal lines through the plurality of first internal vias.