Coplanar Interlaced Capacitor for Multilayer PCB
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Solution Overview
Problem
Capacitors on circuit boards face challenges in increasing capacitance without occupying more space or disrupting impedance matching, as capacitance is proportional to metal layer area and inversely proportional to dielectric layer thickness.
Innovation Solution
A capacitor design with four stacked conductive layers and patterned dielectric layers positioned between each conductive layer, allowing for increased capacitance without altering the capacitor's size, while maintaining impedance matching by using coplanar electrodes and connectors to form positive and negative electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the area of the metal layers is increased to improve capacitance, then the capacitance is improved, but the capacitor occupies much more space
Solution Approach 1:
The patent transitions from a conventional two-layer capacitor structure to a four-layer stacked structure, adding vertical dimensionality. The first and second conductive layers are stacked with dielectric layers between them, effectively doubling the capacitance-generating surfaces without increasing the planar footprint. This dimensional change allows capacitance to be improved while maintaining the same occupied space.
2Quantity of substance
If the thickness of the dielectric layer is decreased to improve capacitance, then the capacitance is improved, but impedance matching with other circuits is affected
Solution Approach 1:
Instead of decreasing dielectric thickness to improve capacitance, the patent adds another dimension by stacking four conductive layers with dielectric layers between them. This approach increases the effective capacitance area without compromising the dielectric thickness, thereby maintaining proper impedance matching with other circuits while achieving higher capacitance.
3Quantity of substance
If four stacked conductive layers are used to increase capacitance without altering size, then capacitance is improved without increasing space, but the device complexity increases
Solution Approach 1:
The capacitor is segmented into four distinct conductive layers (first, second, third, and fourth conductive layers) with dielectric layers positioned between them. Each layer serves a specific function in the capacitive structure, with the first and third layers forming one electrode and the second and fourth layers forming the other electrode. This segmentation allows for increased capacitance through multiple interfaces while maintaining a compact, organized structure that can be efficiently manufactured.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances capacitance without increasing the capacitor's size, allowing it to be integrated into multilayer circuit boards efficiently, saving space and maintaining impedance matching with other circuits.
Implementation Method 1
Capacitance of the capacitor is proportional to an area of the metal layers, and is inversely proportional to a thickness of the dielectric layer
Implementation Method 2
a dielectric layer positioned between the two opposite metal layers
Data Source
AI summary
A capacitor includes a first patterned conductive layer, a second patterned conductive layer and a first patterned dielectric layer. The first patterned conductive layer resembles a comb with internal teeth, and the second patterned conductive layer resembles a comb with external teeth, the internal and the external teeth being interlaced in one plane. A thin first patterned dielectric layer within the same plane is shaped and arranged to infill all the gaps between the teeth. The first patterned conductive layer, the second patterned conductive layer, and the first patterned dielectric layer create a single coplanar layer, and a number of such interconnected coplanar layers are stacked within and contained by a multilayer circuit board.