Co-planar Memory Plane Structure with Shared Sense Amplifiers
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Solution Overview
Problem
Current non-volatile memory devices face challenges in achieving ultra-low read latency due to the need for numerous memory planes, which increases chip size and reduces storage density, making it difficult to maintain both high performance and efficiency.
Innovation Solution
The solution involves partitioning the memory cell region into co-planar memory cell planes with sub-planes and alternating sense amplifier regions, allowing each sense amplifier region to operate with multiple bit lines, thereby reducing bit line capacitance and minimizing the length of bit lines and word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the memory structure is partitioned into numerous memory planes to reduce read latency, then read latency is reduced, but chip size increases and storage density decreases
Solution Approach 1:
Multiple sense amplifier regions are merged into a single shared sense amplifier that serves multiple bit lines across different sub-planes. This consolidation reduces the total periphery circuitry area while maintaining the ability to service multiple memory planes, thereby reducing chip size without sacrificing read latency performance
Solution Approach 2:
The memory structure is segmented into multiple sub-planes within each memory plane, with each sub-plane having a portion of the bit lines served by the shared sense amplifier. This segmentation allows the sense amplifier to efficiently service multiple planes by dividing the bit line load, achieving low read latency without proportionally increasing chip area
2Loss of time
If the memory structure is partitioned into numerous memory planes to reduce read latency, then read latency is reduced, but storage density decreases
Solution Approach 1:
The shared sense amplifier merges multiple sensing functions into a single circuit that can service bit lines from multiple sub-planes and memory planes. This reduces the ratio of periphery circuitry to memory storage, thereby increasing storage density while maintaining ultra-low read latency across all planes
Solution Approach 2:
The shared sense amplifier is designed with multi-functionality to handle sensing operations for multiple bit lines across different memory planes. This universal design allows a single sense amplifier region to perform the work of multiple dedicated sense amplifiers, increasing effective storage density without compromising read performance
3Adaptability or versatility
If per-plane sense amplifier regions are used, then each plane can be independently accessed, but the ratio of periphery circuitry to memory storage increases
Solution Approach 1:
Multiple sense amplifier regions are merged into a single shared sense amplifier that can be selectively activated to service different sub-planes and memory planes. This consolidation dramatically reduces the periphery circuitry area while maintaining the adaptability to independently access any memory plane through selective activation of the shared amplifier
Data Source
AI summary
A non-volatile memory device comprising a memory cell region having a plurality of co-planar memory cell planes arranged in a plane parallel to a semiconductor substrate, with each memory cell plane comprising a plurality of sub-planes disposed adjacent one another along an axis that is parallel to the substrate. Further, each memory cell plane comprises a plurality of sense amplifier regions arranged along the axis in an alternating pattern with the sub-planes such that adjacent to each sub-plane is a sense amplifier region and each sense amplifier region is operable with respect to at least a fraction of the bit lines of the two sub-planes immediately adjacent the sense amplifier region.