Copper Alloy Interconnect Etch Stop via Annealing
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Solution Overview
Problem
Conventional copper interconnect formation methods in semiconductor devices face misalignment issues during photolithography, leading to unstable yield and decreased reliability due to via recesses caused by mask misalignment, which affects the accuracy of successive layer alignment in smaller device dimensions.
Innovation Solution
A method involving the formation of a copper alloy interconnect structure where a copper alloy layer is deposited, annealed to change its etch rate, and then covered with a copper-containing layer with a higher etch rate, allowing precise etching to form interconnect features without undercutting, thereby eliminating via recesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional copper interconnect formation using photoresist mask is used, then the process is simple and widely adopted, but misalignment occurs leading to via recesses and decreased reliability
Solution Approach 1:
The patent changes the etch rate parameter of the copper alloy layer through annealing treatment. By controlling the annealing temperature and atmosphere, the copper alloy's etch rate is reduced to be slower than the overlying copper layer, enabling precise etch stop control and eliminating via recesses caused by mask misalignment.
Solution Approach 2:
The patent uses a composite interconnect structure consisting of a copper alloy layer (e.g., Cu-Sn, Cu-Ni, Cu-Zn) combined with pure copper layers. The copper alloy layer serves as an etch stop layer with controlled etch rate, while the copper layers provide electrical conductivity. This composite approach resolves the misalignment issue while maintaining electrical performance.
2Ease of operation
If conventional copper etching with photoresist mask is used, then the process is straightforward, but via recesses form at the juncture of conductive line and hard mask due to misalignment
Solution Approach 1:
The patent performs preliminary annealing of the copper alloy layer before the final etching step. This preliminary action modifies the copper alloy's microstructure and etch rate characteristics in advance, ensuring that during subsequent etching, the copper layer etches faster than the copper alloy layer, preventing via recess formation even if mask misalignment occurs.
Solution Approach 2:
The copper alloy layer acts as an intermediary between the pure copper layer and the underlying dielectric or hard mask. By positioning the copper alloy layer with controlled etch rate between these layers, it serves as an etch stop that prevents the etch process from penetrating too deeply into the underlying structures, thereby eliminating via recesses.
3Area of moving object
If smaller device dimensions are used, then device density increases, but alignment accuracy between successive layers becomes more critical and difficult to maintain
Solution Approach 1:
The patent changes the etch rate parameter of the copper alloy layer through controlled annealing. This parameter change creates a built-in etch stop mechanism that is insensitive to mask alignment variations, allowing precise pattern transfer even at smaller device dimensions where alignment tolerance is reduced.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures accurate alignment and reliable formation of interconnect features by controlling the etch rate of the copper alloy, reducing misalignment issues and enhancing the stability and reliability of the interconnect structure.
Implementation Method 1
the metal layer is annealed to change the first etch rate to a second etch rate
Data Source
AI summary
A method of manufacturing a semiconductor interconnect structure may include forming a low-k dielectric layer over a substrate and forming an opening in the low-k dielectric layer, where the opening exposes a portion of the substrate. The method may also include filling the opening with a copper alloy and forming a copper-containing layer over the copper alloy and the low-k dielectric layer. An etch rate of the copper-containing layer may be greater than an etch rate of the copper alloy. The method may additionally include patterning the copper-containing layer to form interconnect features over the low-k dielectric layer and the copper alloy.