Copper Wiring in Array Substrates via Merged Mask Processes
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Solution Overview
Problem
The existing manufacturing processes for flat panel display array substrates using copper as a wiring material are complex and costly, requiring multiple photo-mask processes, which increases the difficulty and cost of production while also leading to signal delay issues due to high wiring resistance.
Innovation Solution
An array substrate structure is optimized with a copper metal layer deposited on data and drain electrodes, using a semiconductor active layer of carbon nanotubes or oxide semiconductors, and a gate insulating layer, allowing copper to be used as a wiring material under simpler process conditions through three photo-mask processes, reducing wiring resistance and improving signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper is used as a wiring material on an array substrate, then wiring resistance is reduced and signal transmission is improved, but the number of mask processes increases and manufacturing complexity increases
Solution Approach 1:
The patent combines the formation of the copper wiring layer with the existing transparent electrode layer formation process. The transparent electrode layer (ITO) and copper layer are formed in the same patterning step using a single photo-resist layer, merging two separate manufacturing operations into one. This reduces the total number of mask processes from 7 to 4 while maintaining copper's low resistance benefits for signal transmission.
Solution Approach 2:
The transparent electrode layer serves dual functions: as the pixel electrode in the display region and as the wiring layer (data line and drain electrode) in the transistor region. This multi-functionality allows the same layer to provide both display function and low-resistance copper wiring function, eliminating the need for separate wiring layers and reducing manufacturing steps.
2Ease of manufacture
If the number of photo-mask processes is reduced from 7 to 4, then manufacturing cost is reduced, but the structural design complexity increases
Solution Approach 1:
The array substrate is divided into two functional regions: a transistor region where the transparent electrode layer forms wiring structures (data line and drain electrode), and a pixel region where the same layer forms the pixel electrode. This segmentation allows different parts of the same layer to serve different functions, enabling process simplification without compromising device performance.
Solution Approach 2:
The transparent electrode layer has different local functions: in the transistor region it provides low-resistance copper wiring connections, while in the pixel region it provides the display pixel electrode function. This local differentiation of function within a single layer structure allows the patent to reduce mask processes while maintaining both wiring and display functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of copper as a wiring material in the array substrate reduces wiring resistance and enhances signal transmission performance while minimizing the number of mask processes, thereby lowering production costs.
Implementation Method 1
a copper metal layer deposited on the data line and the drain electrode
Data Source
AI summary
An array substrate includes a pixel structure formed on a substrate. The pixel structure is provided with a transistor region and a pixel region. A source electrode and a drain electrode in the pixel region are located in the transistor region and insulated from each other. A data line is electrically connected to the drain electrode. A pixel electrode is located in the pixel region and electrically connected to the source electrode. A copper metal layer is deposited on the data line and a drain electrode; a semiconductor active layer is formed between the source and drain electrodes and respectively connecting with the source and drain electrodes; a gate insulating layer overlying the data line and the drain electrode. The transparent electrode layer, the copper metal layer and the semiconductor active layer; the gate line and the gate electrode electrically connect to each other on the gate insulating layer.