Copper Doped Hybrid Metallization for Low Resistivity Interconnects
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Solution Overview
Problem
Copper voids at interfaces in semiconductor vias lead to high resistance and failure, with existing processes either reducing voids at the expense of increased resistance in interconnects or failing to maintain low resistivity.
Innovation Solution
A dual copper layer process with varying dopant content, where a first copper layer with a higher dopant content forms a strong interface and a second copper layer with lower or no dopant content fills the via, ensuring low resistivity and improved electro-migration properties, implemented using an integrated tool without vacuum breaks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If critical dimensions are reduced for scaling, then device density is improved, but copper voids increase at interfaces causing via failure
Solution Approach 1:
The patent applies local quality enhancement at the via interface through the first copper layer with dopant, which specifically targets the interface region where voids form during scaling. This localized reinforcement maintains via yield even as critical dimensions are reduced for higher device density.
Solution Approach 2:
The first copper layer with dopant is deposited in advance to establish a void-free interface structure before the second copper layer is added. This preliminary action of creating a robust interface foundation prevents void formation during subsequent processing and scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the quality of copper interfaces, reduces resistivity, and improves time-dependent dielectric breakdown and electro-migration performance, allowing for scaling to sub-30 nm pitch and maintaining low resistance in interconnects.
Implementation Method 1
a first copper layer with a dopant with a first dopant content formed on the liner layer and filling a lower portion of the at least one opening to form a via
Implementation Method 2
enhances the quality of copper interfaces
Implementation Method 3
a second copper layer with the dopant with a second dopant content formed on the first copper layer and filling the at least one opening, where the second dopant content is less than the first dopant content
Implementation Method 4
a barrier layer formed on the sidewall of the at least one opening
Implementation Method 5
a liner layer formed on the barrier layer and on the underlying metallic layer
Data Source
AI summary
Interconnect structures on a substrate have low resistivity and high dopant interfaces. In some embodiments, the structures may have an opening with a sidewall from an upper surface to an underlying metallic layer of copper, a barrier layer of tantalum nitride formed on the sidewall of the opening, a liner layer of cobalt or ruthenium formed on the barrier layer and on the underlying metallic layer, a first copper layer with a dopant with a first dopant content formed on the liner layer and filling a lower portion of the opening to form a via-the first dopant content is approximately 0.5 percent to approximately 10 percent, and a second copper layer with the dopant with a second dopant content formed on the first copper layer and filling the at least one opening—the second dopant content is more than zero to approximately 0.5 percent of the dopant and is less than the first dopant content.