Copper Interconnect Void Filling for Electromigration Resistance
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Solution Overview
Problem
The fabrication of metal interconnect structures in BEOL copper interconnects is challenged by defects such as voids and electromigration, leading to reduced line yield and circuit failures, especially at advanced nodes where patterning becomes difficult and copper grain growth is limited in confined geometries.
Innovation Solution
The method involves forming a metal interconnect layer with buried voids and bamboo microstructures, where the voids are filled with a copper diffusion barrier, and a capping layer is deposited to enhance electromigration reliability and separate the voids from the liner, using techniques like thermal annealing, flash copper deposition, and CMP to planarize the structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper interconnect structures are used in BEOL processing, then electrical resistance is reduced and conduction is improved, but voids and defects form leading to line yield loss and circuit failures
Solution Approach 1:
The patent extracts and removes voids from the copper interconnect structure through a planarization process, separating the defective regions from the functional conductive paths. This extraction eliminates the harmful voids while preserving the beneficial low-resistance copper interconnect structure.
Solution Approach 2:
The patent converts the harmful effect of voids into a beneficial process by using the void regions as targets for selective removal. The planarization process exploits the presence of voids to guide the removal of excess material, transforming a defect into a controlled manufacturing step that improves overall structure quality.
2Reliability
If copper interconnect structures are used, then electromigration occurs leading to structural degradation, but adding capping layers and diffusion barriers increases process complexity
Solution Approach 1:
The patent introduces a diffusion barrier layer as an intermediary between the copper interconnect and the surrounding dielectric material. This intermediary layer prevents direct interaction between copper atoms and the dielectric, blocking electromigration and atomic diffusion while maintaining electrical functionality.
Solution Approach 2:
The patent creates a composite interconnect structure by combining copper with a diffusion barrier layer. This composite structure leverages the high electrical conductivity of copper while the barrier layer provides electromigration resistance, achieving both electrical performance and structural stability.
3Productivity
If advanced node patterning is used to reduce component dimensions, then transistor performance improves, but patterning becomes increasingly difficult and defects increase
Solution Approach 1:
The patent performs preliminary planarization and void removal actions before final interconnect formation. By addressing potential defects early in the manufacturing sequence, the process prevents defect propagation to subsequent steps, making advanced node patterning more manageable.
Solution Approach 2:
The patent changes the physical and chemical parameters of the interconnect structure through controlled planarization and material deposition. By adjusting parameters such as layer thickness, material composition, and processing temperature, the patent optimizes the structure for advanced node requirements while maintaining manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves electromigration reliability, reduces wafer scrap, and achieves a bamboo copper grain structure, even in confined geometries, by forming bamboo microstructures beneath the filled voids, which enhances the performance of copper interconnects.
Implementation Method 1
an electrically conductive filler layer fills the void and comprises a copper diffusion barrier
Implementation Method 2
using techniques like thermal annealing, flash copper deposition, and CMP to planarize the structure
Implementation Method 3
The capping layer is formed with a material that serves to inhibit diffusion, oxidation, and/or electromigration from the top surface of the copper interconnect structures
Data Source
AI summary
Voids within metal deposited on interconnect structures are filled with cobalt or a cobalt compound to enhance electromigration performance. A reflow process to enlarge interconnect metal grain size is performed prior to filling the voids. An interconnect metal microstructure beneath the filled voids includes grain boundaries extending to the bottom portions of the voids. A coating of manganese atoms provides resistance to electromigration. Copper interconnects having fine dimensions and improved reliability are obtained.