Copper Signal Line Silicide Prevention in TFT Array Panels
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Solution Overview
Problem
In flat panel displays, the use of copper signal lines leads to increased resistance due to the formation of copper-silicide when silane gas reacts with the copper surface, causing signal delays and voltage drops, which is exacerbated by the need for additional capping layers that complicate manufacturing.
Innovation Solution
A manufacturing method for liquid crystal displays that forms a gate insulation layer using silicon nitride at controlled temperatures below 280°C, preventing copper-silicide formation by reducing silicon diffusion into copper lines, and employing a double-layer silicon nitride structure with varying binding ratios to manage resistance and maintain low resistivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If copper is used as the signal line material to achieve low resistivity, then the electrical conductivity is improved, but copper-silicide forms during insulating layer formation causing resistance increase
Solution Approach 1:
A capping layer made of refractory metal (molybdenum or its alloy) is introduced as an intermediary between the copper signal line and the silicon-containing insulating layer. This capping layer prevents direct contact and reaction between copper and silicon, thereby preventing copper-silicide formation and maintaining the low resistance of the copper line throughout the manufacturing process and device operation.
2Reliability
If a capping layer is added to prevent copper-silicide formation, then resistance stability is improved, but manufacturing complexity and time increase
Solution Approach 1:
The patent optimizes the thickness of the capping layer to a specific range (50-200 nm) to achieve the necessary protection against copper-silicide formation while minimizing the additional complexity. The refractory metal layer is designed with precise thickness control to provide adequate barrier function without excessive added complexity in the multi-layer structure.
3Reliability
If the capping layer thickness is increased to maintain low resistivity, then resistance stability is improved, but manufacturing time increases
Solution Approach 1:
The patent determines the optimal capping layer thickness range of 50-200 nm through parameter optimization. This thickness is sufficient to prevent copper-silicide formation and maintain resistance stability, while being thin enough to minimize additional manufacturing time and process complexity compared to thicker alternative designs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces the resistance of copper signal lines while maintaining the unique characteristics of low resistivity wiring, thereby improving the performance and efficiency of thin film transistor arrays without significantly increasing manufacturing time.
Implementation Method 1
silane (SiH4) gas may react with the surface of a copper (Cu) line during a process of forming an insulating layer on the copper line, and accordingly copper-silicide (Cu-silicide) is formed
Implementation Method 2
forming a gate insulation layer by supplying a gas which includes silicon to the gate electrode
Implementation Method 3
employing a double-layer silicon nitride structure with varying binding ratios to manage resistance and maintain low resistivity
Data Source
AI summary
A manufacturing method of a thin film transistor (TFT) includes forming a gate electrode including a metal that can be combined with silicon to form silicide on a substrate and forming a gate insulation layer by supplying a gas which includes silicon to the gate electrode at a temperature below about 280° C. The method further includes forming a semiconductor on the gate insulation layer, forming a data line and a drain electrode on the semiconductor and forming a pixel electrode connected to the drain electrode.