Solid-State Devices TRIZ Cases

Retro-stepped dielectric material enables varying support pillar heights, reducing manufacturing complexity and improving areal density.

Silicon-doped amorphous carbon electrodes maintain optimal resistivity across temperature ranges in phase change memory devices.

A fluoride layer protects the nitride fluorescent material core from oxygen and moisture, preserving chromaticity under high temperature and humidity.

A pixel circuit embeds capacitors between conductive layers to secure required capacitance without increasing area.

Selective cladding of doped core regions in GaN fin structures reduces lattice mismatch defects while enabling efficient RGB color emission.

Horizontal alignment of optical devices with waveguides eliminates micro mirrors and lenses, reducing light loss and manufacturing complexity.

Graphite separation layers allow parallel cutting of carrier wafers, reducing production costs for non-silicon semiconductor devices.

Deep grooves with continuous light reflection shielding layers in CMOS image sensors prevent optical crosstalk between adjacent pixels.

A pixel structure fabricating method uses inkjet printing to deposit color filter layers on thin film transistor substrates.

An anisotropic conductive layer electrically connects a micro-LED chip to a substrate while preventing short-circuits between adjacent chips.

Varying air gap heights lower parasitic capacitance to improve electric characteristics while preventing exposure during contact plug formation.

Higher work function conductive cover layers suppress fringing fields to prevent charge accumulation in inter-cell areas, improving data retention.

A memory device selects precharge paths based on sub-block positions relative to select lines.

A gate insulation layer forms at low temperatures to protect copper signal lines from silicide reactions during thin film transistor manufacturing.

Recesses with a functional layer containing light emission within sub-pixels, reducing optical cross-talk that blurs images.

A pixel structure incorporates a charge releasing device to manage electrical potential across floating electrodes.

An array substrate adjusts pixel density and electrode shapes to improve brightness uniformity across display panels.

Varying ink application volumes in peripheral gaps compensates for differential solvent evaporation rates, reducing luminance unevenness.

An anti-peeping display device integrates an interference module emitting polarized light with a standard panel to generate unreadable images for unauthorized viewers.

Tilting pixel array directions relative to the semiconductor substrate cleavage direction prevents thermal expansion cracks and enhances device rigidity.

A window member uses a resin layer covering a pattern layer to prevent detachment during cleaning.

A hole injection layer uses two host materials with a 0.2 eV HOMO energy difference to optimize charge balance in organic light emitting devices.

Physical plasma etch clean-up process removes conductive residues from ferroelectric capacitor sidewalls.

Etched substrate regions expose front-side alignment marks for backside optical detection, resolving wafer registration challenges during backside patterning.

Epitaxial germanium growth on silicon improves carrier mobility while preliminary isolation layer formation prevents shallow trench isolation holes.

A semiconductor device with a specific n-type impurity concentration distribution in pillar and barrier regions.

A magnetic memory cell merges read and write current paths through a shared nonmagnetic layer to shrink the footprint of spin-orbit torque devices.

Asymmetric aperture masks on cyclic photoelectric element groups capture horizontal and vertical parallax, eliminating the need for multiple imaging devices.

Alternating transparent layers reflect ultraviolet laser energy to prevent damage to thin film transistors during lift-off and annealing.

Nesting two ESD stages vertically within a single trench reduces layout complexity and prevents gate oxide damage.

A mixed liquid of a water repellency agent and resist-soluble chemical forms a protective film on semiconductor patterns.

A pixel electrode frame and common electrode groove structure weaken electric field interference on the branch.

Fluid ablation removes backside layers from plasma-diced singulation lines, resolving the trade-off between high throughput and effective layer removal.

Vertical bit line semiconductor memory device arranges select gate control lines between local bit lines to reduce short circuiting and misalignment.

Segmented multi-layer wiring and via structures distribute mechanical stress to prevent titanium-aluminum-titanium wiring breakage during bending.

Siloxane and silane interfacial layers increase mobility by 50% while reducing fabrication complexity compared to silicon processes.

Depositing a high-k dielectric layer over the absorption structure activates dopants during deposition, eliminating ion implantation steps.

Segmenting the channel layer and applying a negative bias via a transparent upper electrode stabilizes the threshold voltage against light-induced stress.

Asymmetric cell orientation and local quality maintain monotonicity across hundreds of elements, resolving routing-induced delay variance.

Integrates infrared radiation cut layers into CMOS image sensor color filter assemblies, eliminating bulky optical shutters and reducing module size.

A semiconductor upper contact plug uses a damascene second metal pattern contacting the first metal pattern sidewall.

A laminated display structure positions light-emitting diodes to overlap specific thin film transistor circuits while avoiding sensitive channel regions.

A pixel structure forms a storage capacitor using a third conductive layer, passivation layer, and second conductive layer to increase aperture ratio.

A composite reflective layer with TiO2 particles increases reflectance while a boundary element protects the chip mounting area from corrosion.

Planarized inorganic encapsulation layers on a display panel improve moisture permeability resistance and optical properties by sealing light emitting elements.

A disabling mechanism identifies and isolates defective flash memory dies within multi-die packages to preserve functional storage capacity.

Specific host-guest combinations resolve the trade-off between high luminous efficiency and short phosphorescent material lifespan.

Composite thin film encapsulation reduces moisture permeability to extend organic light emitting device life without adding significant weight.

Segmenting the hole transport region prevents exciton quenching at interfaces, extending device lifespan and lowering driving voltage.

A nitride barrier layer sits between the element isolation insulating film and the block film.

A screen covers the protruding carrier edge of an OLED or QLED module, resolving the contradiction between mounting reliability and visual homogeneity.

Vertical stacking of data lines expands surface area, lowering impedance to fix uneven charging in high-resolution displays.

A poly-silicon and oxide semiconductor thin-film transistor array substrate reduces pixel circuit size.

A segmented LED array with individual reflectors and separated phosphor layers directs light mixing through asymmetric optical structures.

LTCC substrate slots reduce coupling between microstrip fed dipoles, achieving 10 dB gain and isolating endfire antennas for full-duplex operations.

A thin film transistor array panel uses an organic insulator with varying thicknesses to cover color filters and support light blocking members.

Sequential gas etching replaces chemical mechanical polishing to resolve dishing defects in semiconductor memory capacitors while maintaining process margins.

Fully integrated avalanche photodiode receiver merges passive components on silicon-on-insulator substrate to reduce parasitic effects.

Organic protrusions in inorganic layer openings reduce stress concentration, preventing crack propagation and peeling during manufacturing.

A top emitting organic electroluminescent device uses scattering layers to redirect light propagation paths.

Adjusting the load resistor prevents diode breakdown and restores short-circuited ReRAM cells.

A semiconductor structure uses a conductive strip with distinct conductivity characteristics supported by a dielectric layer and plug.

A composite cathode structure integrates a conductive layer within an oxidation-formed protection layer to enhance electrical conductivity in organic electroluminescent displays.

Thiazole-containing polymers shift absorption toward red light, resolving the trade-off between electrode conductivity and light transmission.

A semiconductor memory device applies distinct pre-charge voltages to dummy word lines adjacent to the joint portion of stacked memory pillars.

Dual-island ion implantation reduces photomask count and fabrication time for TFT-LCD transistors while maintaining doping precision.

Spacer-assisted particle extraction removes metal re-deposition between MRAM pillars, reducing cell-to-cell leakage.

Continuous semiconductor formation eliminates contact resistance between joined columnar structures, preventing insulating layer damage during manufacturing.

A segmented filament storage element obtains at least three resistance states by changing layer combinations.

Varying passivation layer thickness adjacent to electrode slits prevents short-circuits between sub-electrodes while maintaining pixel connectivity.

Silicon nitride pull-back etch prevents voids and contact resistance issues in high-density trench capacitors.

A light emitting diode features a concave base housing an LED chip over arc-shaped reflective layers to direct light toward side directions.

Four-phase spinning interchanges terminals to average out dielectric polarization errors, improving magnetic field measurement accuracy.

A flat second source-drain electrode surface enables stable touch electrode line connections in flexible displays.

Stacking transistors vertically increases integration density without shrinking feature sizes.

A dual-layer display apparatus uses separate substrates to produce independent images on opposing surfaces without optical interference.

A photonic crystal optical coupler redirects radiation toward photoluminescent blocks to enhance conversion efficiency.

Shared fuse circuits resolve chip area trade-offs by enabling precise TSV replacement in 3D integrated devices.

A charge directing switch routes packets to a multiplying register or bypass path, preventing blooming in bright regions while amplifying small signals.

Organic nanobiomimetic memristors detect sub-pM amyloid-beta concentrations without antibodies, resolving instability in biological fluid analysis.

Segmenting the device into a selection transistor and a charge storage transistor avoids high-k material charge trapping, enhancing retention capacity.

Pyrolysis removes a polymer template to form air gaps between color filters, reducing light reflection and scattering for higher optical sensitivity.

Lift-off deposition of silver within via openings eliminates metal etching defects that compromise device reliability in non-volatile memory fabrication.

Single mask fabrication reduces Mura defects and off-currents by merging semiconductor patterning with chemical-mechanical polishing.

Segmented electro-optic devices with perpendicular insulating structures achieve high speed modulation by resolving refractive index variation trade-offs.

Vertical stacking and segmentation simplify interconnections while reducing chip size in variable resistance memory devices.

Soldering thin semiconductor circuits to a support substrate enables safe detachment from the silicon base, preventing mechanical damage during transfer.

Segmenting the emitter into a parallel array resolves the trade-off between response time and illumination intensity in optical communication.

Insulating core bottom electrode fills gaps to ensure planar topography and reliable data storage.

Ion implantation and solid phase epitaxial regrowth form a strained silicon layer, replacing expensive ultra high vacuum chemical vapor deposition processes.

Stacking vertical pass transistors above the memory cell array in a stair area resolves the contradiction between increased integration and expanded chip size.

A non-volatile memory device uses a charge spread blocking layer between stacked gate electrodes to prevent leakage.

Virtual grid lines align standard cell input output ports with metal routing paths, reducing additional metal layer requirements.

Diagonal junction regions in a buried bit line structure prevent floating body effects by ensuring proper body bias application to vertical channel transistors.

Forming a photosensitive adhesive layer on the bending region protects peripheral circuits from cracking and disconnection when the thin base substrate folds.

A semiconductor memory device uses a control logic circuit to store parity data in a dedicated cell region alongside main data.

An internal third electrode reduces electromagnetic noise from high voltage, preserving detection sensitivity.

Block power switch integrates ESD protection circuitry with adaptive body biasing to manage leakage current.

Polyelectrolyte end groups fill surface defects in quantum dot light-emitting diode electron transport layers.