Semiconductor Memory Air Gap Design for Parasitic Capacitance Reduction
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Solution Overview
Problem
The increasing demand for high-speed and reliable semiconductor memory devices with decreasing pattern sizes poses challenges in achieving improved electric characteristics, as smaller feature sizes complicate the realization of high operating speeds and reliability.
Innovation Solution
The semiconductor memory device incorporates a design with air gaps between active regions and gate electrodes, formed by a method involving sacrificial layers, porous insulating layers, and etching processes, which allows for the creation of varying air gap heights to optimize electric characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If pattern size is decreased to increase integration density, then device miniaturization is achieved, but electric characteristics and reliability deteriorate
Solution Approach 1:
An air gap is introduced as an intermediary structure between adjacent patterns to reduce parasitic capacitance. The air gap acts as a dielectric medium with lower permittivity than conventional insulating materials, thereby improving electric characteristics and signal integrity while maintaining miniaturized dimensions
Solution Approach 2:
The air gap height is varied locally depending on the specific region and functional requirements. Different air gap heights are implemented in different areas to optimize electric characteristics for specific circuit functions while maintaining overall device miniaturization
2Reliability
If air gap is formed to improve electric characteristics, then parasitic capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
A sacrificial layer is deposited and patterned before forming the final insulating structure. This preliminary sacrificial layer defines the air gap region and is subsequently removed to create the desired air gap geometry, simplifying the overall manufacturing process
Solution Approach 2:
The sacrificial layer is selectively removed from the structure to create the air gap. This extraction process is achieved through selective etching that removes only the sacrificial material while leaving the surrounding insulating layers intact, thereby forming the air gap without complex direct fabrication steps
3Reliability
If air gap height is increased to reduce parasitic capacitance, then electric characteristics improve, but risk of air gap exposure increases
Solution Approach 1:
The insulating layer is extended over the trench containing the air gap to provide protective coverage. This cushioning structure prevents air gap exposure during subsequent processing steps such as contact plug formation while still allowing the air gap to function for reducing parasitic capacitance
Solution Approach 2:
The insulating layer is formed to extend in the vertical dimension over the trench, providing top-down protection of the air gap. This dimensional extension ensures that the air gap remains protected during contact plug formation and other processing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the electric characteristics of semiconductor memory devices by reducing parasitic capacitance and improving performance, while preventing air gap exposure during contact plug formation, thus enhancing reliability and preventing electric failures.
Implementation Method 1
forming a porous insulating layer on the sacrificial pattern, removing the sacrificial pattern through pores of the porous insulating layer to form an air gap in the trench
Data Source
AI summary
Provided are a semiconductor memory device and a method of fabricating the same. the semiconductor memory device may include a semiconductor substrate with a first trench defining active regions in a first region and a second trench provided in a second region around the first region, a gate electrode provided on the first region to cross the active regions, a charge storing pattern disposed between the gate electrode and the active regions, a blocking insulating layer provided between the gate electrode and the charge storing pattern and extending over the first trench to define a first air gap in the first trench, and an insulating pattern provided spaced apart from a bottom surface of the second trench to define a second air gap in the second trench.