Stacked ESD Network in Trench for DMOS Layout
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Solution Overview
Problem
Trench DMOS devices face challenges with electrostatic discharge (ESD) protection due to shrinking die size and intrinsic ESD capability, requiring complex layouts and metal routing for two stages of ESD diodes with resistors, which complicates manufacturing and increases the risk of gate oxide damage.
Innovation Solution
A stacked ESD network is placed inside the trench, comprising heavily doped substrates, epitaxial layers, oxide layers, and multiple poly layers with back-to-back diodes and resistors, allowing for simple metal routing and enhanced ESD protection without the need for additional topology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two stages of ESD diodes with resistor are used to handle higher ESD voltage, then ESD protection capability is improved, but device complexity and layout complexity increase
Solution Approach 1:
The patent implements two stages of ESD diodes by nesting them within a single trench structure. The first poly layer contains a first pair of back-to-back diodes, while the second poly layer contains a second pair of back-to-back diodes with a resistor, both stacked vertically within the same trench. This nesting approach provides enhanced ESD protection capability while avoiding the need for separate layout areas for each ESD stage, thereby reducing layout complexity.
Solution Approach 2:
The patent transitions from a planar two-stage ESD structure to a vertical three-dimensional stacked structure. By stacking the first and second poly layers with their respective ESD diodes and resistor vertically within the trench, the design utilizes the vertical dimension to accommodate multiple ESD stages. This dimensional change reduces the horizontal layout area and simplifies metal routing while maintaining the two-stage ESD protection functionality.
2Reliability
If ESD structure is formed in the poly layer at Gate pad, then ESD protection is provided, but topology becomes non-flat and masking layer like contact masking becomes difficult
Solution Approach 1:
The patent nests the ESD structure within the trench that already exists in the Trench DMOS device. By forming the first and second poly layers with ESD diodes inside the trench, the design avoids adding extra topology on the gate pad surface. This nesting approach maintains a flat overall topology while providing comprehensive ESD protection, and simplifies subsequent masking processes such as contact masking.
Solution Approach 2:
The patent merges the ESD structure formation with the existing trench structure. The ESD diodes are formed within the same trench that houses the DMOS device, combining two functions into a single structural element. This merging eliminates the need for separate ESD structure formation on the gate pad, maintaining flat topology and simplifying manufacturing processes.
3Productivity
If die size is shrunk to advance technology, then device integration is improved, but intrinsic ESD capability decreases
Solution Approach 1:
The patent utilizes the vertical dimension within the trench to stack multiple ESD diodes and a resistor, creating a compact three-dimensional ESD protection network. This vertical stacking allows two complete stages of ESD protection to be accommodated within a small horizontal footprint, enabling enhanced ESD capability in shrunk die sizes while maintaining high device integration.
Solution Approach 2:
The patent nests multiple ESD diodes and resistors within the trench structure, maximizing the use of available space. By placing the first and second poly layers with their respective ESD diodes and resistor inside the trench, the design achieves compact ESD protection that scales well with reduced die size, maintaining intrinsic ESD capability despite technology scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stacked ESD structure provides effective ESD protection with a flat topology and simplified metal routing, addressing the limitations of shrinking die size and intrinsic ESD capability while preventing gate oxide damage.
Implementation Method 1
an oxide layer formed on an inner sidewall of the trench
Implementation Method 2
a heavily doped substrate acting as a drain; an epitaxial layer grown on the substrate
Data Source
AI summary
A stacked ESD structure comprises a heavily doped substrate; an epitaxial layer grown on the substrate; a trench formed in the epitaxial layer; an oxide layer formed on an inner sidewall of the trench; first and second poly layers formed in the trench; a plurality of P-type regions and N-type regions formed inside the first and second poly layers to make back to back diodes in the first and second poly layers respectively; a dielectric layer formed in the trench, between the first and second poly layers; an insulating layer formed on top of the second poly layer and the trench; a plurality of contact defined to connect the first poly layer, the poly resistor and the second poly layer, through the insulating layer; and a metal layer formed on top of the insulating layer.