Semiconductor Device N-Type Impurity Distribution for Latch-Up Prevention

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Solution Overview

Problem

The existing semiconductor devices face challenges in preventing latch-up and improving reverse recovery characteristics due to high n-type impurity concentration in the barrier region, leading to high resistance and potential for parasitic npn transistor activation.

Innovation Solution

The semiconductor device design includes a trench structure with a gate insulating film and a specific n-type impurity concentration distribution in the pillar and barrier regions, where the n-type impurity concentration is reduced in the barrier region by deeper implantation and diffusion, and a p-type lower body region is formed to separate the barrier and drift regions, preventing high electric fields at the body region corners.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If the n-type impurity concentration in the barrier region is high, then the barrier region can effectively block current, but the depletion layer broadly extends in the body region causing high resistance

Engineering Contradiction:
Improvecurrent blocking capabilityVSAvoidbody region resistance control
Core Design Contradiction:
StrengthVSManufacturing precision

Solution Approach 1:

The patent implements local quality by establishing distinct n-type impurity concentration zones. The barrier region maintains a higher first n-type impurity concentration to ensure effective current blocking, while the drift region is designed with a lower second n-type impurity concentration to control depletion layer extension and maintain acceptable body region resistance. This localized optimization resolves the contradiction between current blocking capability and resistance control.

Inventive Principle:
Principle #3Local quality

2Reliability

If the n-type impurity concentration in the barrier region is high, then the pn-junction is effectively blocked, but the parasitic npn transistor is more likely to be turned on

Engineering Contradiction:
Improvepn-junction blockingVSAvoidparasitic npn transistor activation
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies local quality by differentiating n-type impurity concentrations between the barrier region and drift region. The barrier region's higher first n-type impurity concentration ensures effective pn-junction blocking, while the drift region's lower second n-type impurity concentration reduces the likelihood of parasitic npn transistor activation. This spatial variation in impurity concentration addresses both requirements simultaneously.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design reduces the likelihood of latch-up and enhances avalanche resistance by minimizing n-type impurity concentration in the barrier region, thereby improving the semiconductor device's performance and reliability.

Implementation Method 1

an n-type impurity concentration distribution in a depth direction in the pillar region and the barrier region has a maximum value in the pillar region. Further, the n-type impurity concentration distribution has a folding point on a side deeper than the maximum value in the pillar region in the depth direction

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Implementation Method 2

the n-type impurity concentration distribution in a depth direction in the pillar region and the barrier region has a maximum value in the pillar region. Further, the n-type impurity concentration distribution has a folding point on a side deeper than the maximum value in the pillar region in the depth direction

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentUS9620632B2Semiconductor device and method of manufacturing the semiconductor device
Publication Date: 2017.04.11 DENSO CORP
  • US9620632B2 patent drawing
  • US9620632B2 patent drawing
  • US9620632B2 patent drawing

AI summary

A semiconductor device includes: a semiconductor substrate, an upper electrode, a lower electrode and a gate electrode. In the semiconductor substrate, a body region, a pillar region, and a barrier region are formed. The pillar region has an n-type impurity, is formed on a lateral side of the body region, and extends along a depth from a top surface of the semiconductor substrate to a lower end of the body region. The barrier region has an n-type impurity and is formed on a lower side of the body region and the pillar region. The barrier region is formed on the lower side of the pillar region. An n-type impurity concentration distribution in a depth direction in the pillar region and the barrier region has a maximum value in the pillar region. The n-type impurity concentration distribution has a folding point on a side deeper than the maximum value.