Memory Sub-Block Precharge Path Selection for Partial Erase
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Solution Overview
Problem
Existing memory devices with three-dimensional nonvolatile memory cell arrays face challenges in efficiently managing memory operations, particularly in performing partial erase operations and ensuring data reliability due to the complexity of sub-block positioning and operation methods.
Innovation Solution
The proposed method involves a memory device with sub-blocks connected to common source lines and bit lines, where a memory controller determines the position of sub-blocks to select appropriate precharge paths and program sequences for operations, allowing for efficient precharge, program, and read operations based on the sub-block's position relative to string select lines and ground select lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional two-dimensional array structure is used, then the memory device is simpler to manage, but it cannot efficiently handle large memory blocks and partial erase operations
Solution Approach 1:
The memory block is divided into multiple sub-blocks, each independently manageable. This segmentation allows partial erase operations to be performed on specific sub-blocks without affecting the entire memory block, thereby improving productivity in managing large memory blocks while maintaining a structured approach that doesn't excessively increase device complexity
2Reliability
If precharge operations are performed without considering sub-block positions, then the operation process is simpler, but interference occurs during precharge operations affecting data reliability
Solution Approach 1:
The precharge operation is differentiated based on the position of sub-blocks relative to string select lines and ground select lines. Sub-blocks adjacent to string select lines receive precharge through bit lines, while other sub-blocks are precharged through the common source line. This localized approach to precharging eliminates interference and improves data reliability without requiring complex global control mechanisms
3Reliability
If uniform program sequences are used for all sub-blocks, then the control process is simpler, but interference during operations reduces data reliability
Solution Approach 1:
Different program sequences are applied to different sub-blocks based on their positions. Sub-blocks adjacent to string select lines are programmed in one sequence, while other sub-blocks are programmed in a different sequence. This localized differentiation eliminates operational interference and improves data reliability, with the complexity managed through systematic position-based classification
Data Source
AI summary
A memory device can include a memory block operatively connected to a common source line and a plurality of bit lines, wherein the memory block includes first and second sub-blocks each having a respective position in the memory block relative to the common source line and the plurality of bit lines. The memory device can be operated by receiving a command and an address from outside the memory device and performing a precharge operation on the memory block in response to the command, using a first precharge path through the memory block or a second precharge path through the memory block based on the respective position of the first or second sub-block that includes a word line that is configured to activate responsive to the address.