Semiconductor Memory Device Select Gate Control Line Short Circuiting
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Solution Overview
Problem
Existing semiconductor memory devices with VBL structures face challenges in reducing short circuiting between select gate control lines and misalignment issues, leading to decreased cell occupancy rates and increased chip area.
Innovation Solution
The semiconductor memory device employs a VBL structure with select gate control lines disposed between local bit lines in the X-direction, reducing short circuiting and allowing for batch processing of local bit lines and select gates, thereby improving cell occupancy rates and reducing chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If select gate control lines are arranged in conventional VBL structure, then device complexity is reduced, but short circuiting occurs between control lines and misalignment issues arise
Solution Approach 1:
The patent transitions from conventional planar arrangement of select gate control lines to a three-dimensional stacked configuration where control lines are arranged in different layers (first select gate control lines in one layer, second select gate control lines in another layer). This dimensional change allows control lines to be positioned above or below each other vertically, eliminating short circuiting and misalignment issues while maintaining device functionality.
2Productivity
If conventional bit line and select gate arrangement is used, then manufacturing process is simpler, but cell occupancy rate decreases and chip area increases
Solution Approach 1:
The patent employs a three-dimensional stacked architecture where memory cells are arranged in multiple layers vertically. Local bit lines extend in the first direction and select gates extend in the second direction perpendicular to the first direction, with control lines positioned in different vertical layers. This vertical stacking enables higher cell density within the same chip footprint, improving cell occupancy rate without increasing chip area.
Solution Approach 2:
The patent implements a nested configuration where multiple functional elements are stacked vertically - local bit lines, select gates, and control lines are positioned in different layers, with each layer containing multiple cells. This nesting approach allows multiple memory cells to occupy the same horizontal footprint by stacking them vertically, thereby increasing cell occupancy rate while reducing required chip area.
Data Source
AI summary
A semiconductor memory device according to an embodiment includes: a first wiring line extending in a first direction; a second wiring line extending in a second direction, the second direction intersecting the first direction; a variable resistance film disposed at an intersection of the first wiring line and the second wiring line; a channel body disposed at a first end of the first wiring line; a third wiring line electrically connected to the first wiring line via the channel body; and a gate wiring line extending in the first direction and facing the channel body from the second direction.