Upper Contact Plug Damascene Process for DRAM Integration
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Solution Overview
Problem
As the integration density of DRAM devices increases, the reduced distance between bit line structures narrows the process margin for etching the upper contact plug layer, making it challenging to form well-spaced upper contact plugs that are electrically connected to capacitors without misalignment or insufficient spacing.
Innovation Solution
The semiconductor device incorporates a method where an upper contact plug is formed using a damascene process, with a second metal pattern contacting both the upper surface and sidewall of a first metal pattern, and a barrier pattern covering the lower surface and sidewall of the first metal pattern, ensuring proper electrical connection and spacing between bit line structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the integration degree of the DRAM device increases, then the density and capacity of the device improve, but the distance between bit line structures decreases, causing the process margin for etching the upper contact plug layer to decrease
Solution Approach 1:
The patent performs preliminary actions by forming the lower contact plug and first metal pattern before forming the upper contact plug. The lower contact plug is formed first, followed by the first metal pattern on top of it, and then the upper contact plug is formed later in the process. This sequential preliminary action allows each layer to be optimized independently, compensating for the reduced process margin caused by higher integration density.
Solution Approach 2:
The contact plug structure is segmented into multiple distinct layers: lower contact plug, first metal pattern, and upper contact plug. Each segment serves a specific function and can be formed with different materials and dimensions. This segmentation allows the etching process for the upper contact plug layer to be controlled more precisely, addressing the reduced process margin issue while maintaining high integration density.
2Area of stationary object
If the distance between bit line structures decreases to increase integration, then the device density improves, but the spacing and alignment control for forming upper contact plugs becomes more difficult
Solution Approach 1:
The patent applies local quality by making the first metal pattern extend beyond the upper contact plug opening in certain regions. Specifically, the first metal pattern has a wider lower portion that extends laterally beyond the opening, while the upper portion is removed to form the upper contact plug. This local variation in the metal pattern geometry provides alignment tolerance and ensures proper electrical connection even with reduced spacing between bit line structures.
Solution Approach 2:
The patent addresses alignment control by transitioning from a two-dimensional planar contact structure to a three-dimensional multi-layer structure. The vertical stacking of lower contact plug, first metal pattern, and upper contact plug provides an additional dimensional degree of freedom for alignment compensation. The etching process can be controlled in the vertical dimension while the lateral dimensions benefit from the extended first metal pattern geometry.
3Reliability
If the upper contact plug layer is etched to form upper contact plugs, then the electrical connection to capacitors is established, but the reduced process margin causes insufficient spacing or misalignment
Solution Approach 1:
The lower contact plug and first metal pattern are formed as preliminary structures before the upper contact plug etching process. The first metal pattern is formed with dimensions that anticipate the subsequent etching step, extending beyond the final upper contact plug opening. This preliminary configuration ensures that even with reduced process margin, the etching will result in properly spaced and aligned upper contact plugs with reliable electrical connections.
Solution Approach 2:
The first metal pattern serves as a cushioning structure by extending beyond the upper contact plug opening. This extra material provides a buffer zone that compensates for potential etching variations. If the etching process deviates from ideal conditions, the extended first metal pattern ensures that the upper contact plug still maintains proper spacing and alignment, preventing misalignment and insufficient spacing issues.
Data Source
AI summary
A semiconductor device includes a bit line structure on a substrate, a lower contact plug on a portion of the substrate adjacent to the bit line structure, an upper contact plug including a first metal pattern on the lower contact plug and a second metal pattern contacting an upper surface and an upper sidewall of the first metal pattern, and a capacitor on the upper contact plug. The upper surface of the first metal pattern is above an upper surface of the bit line structure with respect to an upper surface of the substrate.