Capacitive Structure for Pixel Circuit Size Reduction
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Solution Overview
Problem
Existing electro-optical devices face challenges in maintaining image quality due to variations in transistor threshold voltages, leading to increased circuit size and cost when compensating for capacitance issues in miniaturized pixel configurations.
Innovation Solution
The electro-optical device incorporates a capacitive structure with conductive layers and dielectric films to form capacitors within the pixel circuit, allowing for the securement of required capacitance without increasing the circuit size, by strategically placing capacitors between conductive layers and using shared data transfer lines to distribute capacitance efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a capacitance element is added to the data line outside the pixel to compensate for capacitance deficiency, then the required capacitance is secured, but the circuit size increases and cost increases
Solution Approach 1:
The patent embeds the capacitance element within the pixel circuit structure by forming it between the data transfer line and a conductive layer in the same pixel, rather than adding it externally. This nesting approach allows the capacitance element to occupy space already allocated for pixel components, thus providing the necessary capacitance compensation without increasing the overall circuit size or cost
Solution Approach 2:
The patent utilizes the vertical stacking of conductive layers to create the capacitance element. By forming the capacitance element between different conductive layers (data transfer line and another conductive layer) separated by an insulating film in the vertical dimension, rather than expanding horizontally, the patent achieves capacitance compensation within the existing pixel footprint, effectively using the third dimension to resolve the space constraint
2Area of stationary object
If the pixel circuit is miniaturized to reduce device size, then the device becomes more compact, but capacitance deficiency occurs
Solution Approach 1:
The patent resolves the capacitance deficiency in miniaturized pixels by transitioning from a planar capacitance layout to a vertically stacked configuration. The capacitance element is formed between conductive layers separated by an insulating film in the vertical dimension, allowing sufficient capacitance to be achieved within the reduced horizontal pixel area, thus enabling pixel miniaturization without sacrificing capacitance performance
Solution Approach 2:
The patent integrates the capacitance element within the miniaturized pixel structure by nesting it between existing conductive layers (data transfer line and another conductive layer) using the vertical space within the pixel. This nested configuration provides the required capacitance without increasing the horizontal pixel dimensions, thus maintaining the miniaturized form factor while ensuring adequate capacitance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively secures necessary capacitance within the pixel circuit, maintaining image quality while minimizing the circuit's size and cost, and reduces noise effects on the transistor gates, thereby enhancing display performance.
Implementation Method 1
a first capacitor that includes a fourth conductive layer which is coupled to the second conductive layer, a fifth conductive layer which is coupled to the third conductive layer, and a dielectric film between the fourth conductive layer and the fifth conductive layer
Implementation Method 2
a dielectric film between the fourth conductive layer and the fifth conductive layer
Implementation Method 3
a sixth conductive layer that shields the second conductive layer
Data Source
AI summary
An electro-optical device includes a first electrode that is coupled to a first data transfer line, a second electrode that is coupled to a second data transfer line. The first and second electrodes are respectively formed in different layers. A first capacitor is formed of the first electrode, the second electrode, and a dielectric film between the first electrode and the second electrode. In addition, a power supplying line and the first data transfer line are formed in a same layer. A second capacitor is formed of the power supplying line, the first data transfer line, and an insulating layer between the power supplying line and the first data transfer line.