Semiconductor Delay Chain Monotonicity via Asymmetric Cell Orientation
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Solution Overview
Problem
Existing delay chains in semiconductor devices face challenges in maintaining monotonicity across hundreds of delay elements, particularly due to routing impacts that can break the monotonicity of successive delays.
Innovation Solution
A semiconductor device with a delay chain integrated into a semiconductor layer, featuring a plurality of delay cells connected to supply and reference voltage metal lines, where each delay cell is oriented transversely to these lines and interconnected in a staggered arrangement to ensure consistent delay across the chain, with programmable cells controlling signal switching between paths to maintain monotonicity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a delay chain with hundreds of delay elements is implemented using conventional routing, then the delay chain can provide multiple delay values, but the monotonicity of delays along the chain cannot be assured due to routing impacts
Solution Approach 1:
The patent applies asymmetry by orienting all delay cells in the same directional direction (e.g., all facing upward or all facing downward), while the metal lines are arranged asymmetrically with respect to the delay cells. This asymmetric arrangement ensures that routing impacts are consistent across all delay elements, thereby maintaining monotonicity of delays along the chain while still providing multiple selectable delay values.
2Area of stationary object
If delay cells are arranged in a compact layout to reduce area, then the device size is reduced, but routing impacts may break the monotonicity of successive delays
Solution Approach 1:
The patent applies local quality by ensuring that each delay cell has the same local orientation and configuration relative to the metal lines. Each delay cell is positioned and oriented in a consistent manner (e.g., all cells oriented perpendicular to the metal lines in the same direction), which ensures uniform routing impacts locally at each cell, thereby maintaining global monotonicity while achieving compact layout.
3Adaptability or versatility
If a multiplexer and controller are added to select desired delay, then the delay chain becomes programmable, but the device complexity increases
Solution Approach 1:
The patent merges the delay chain functionality with the selection mechanism by integrating the multiplexer and controller directly into the delay chain structure. The controller is coupled to receive a control signal and selectively activate specific delay elements within the chain, combining the delay generation and selection functions into a unified integrated structure, thereby reducing overall device complexity while maintaining programmability.
Data Source
AI summary
A semiconductor device wherein a delay chain is integrated; the semiconductor device having a semiconductor layer. The delay chain includes a plurality of delay cells placed in the semiconductor layer and electrically connected to each other so as to form the delay chain. The semiconductor device includes a first and second metal lines respectively connected to a supply voltage and a reference voltage and placed in a longitudinal direction on a surface of the semiconductor layer; each delay cell of the plurality of cells is electrically connected with the first and second metal lines. Any delay cell and its successive or preceding delay cells of the delay chain are placed in a transversal direction with respect to the first or the second metal line.