Wafer-Level Packaging Using Copper-Tin SLID Frames
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Solution Overview
Problem
Conventional packaging methods for electrical circuits, such as bolometers, are costly, inefficient, and difficult to manufacture due to the need for precise thermal isolation and the use of expensive materials, with limitations in flexibility and scalability, especially when dealing with microbolometer arrays where the lid and substrate wafers must be of equal size and require complex vacuum processes.
Innovation Solution
A method involving the use of a frame with a layer sequence of copper and tin for solid liquid interdiffusion (SLID) to connect substrates, allowing for precise adjustment of the distance between them and enabling efficient packaging of functional electrical circuits at the wafer level, where only functional circuits are packaged with a smaller lid substrate, and the connection is made in a vacuum to create a self-contained volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging methods are used for bolometers, then thermal isolation of the membrane is achieved, but manufacturing cost and complexity increase significantly
Solution Approach 1:
The patent combines the substrate and lid wafer into a single integrated structure where the lid wafer serves both as a mechanical cover and as part of the thermal isolation system. The frame structure integrates multiple functions including mechanical support, thermal isolation, and vacuum sealing, eliminating the need for separate packaging components and reducing manufacturing complexity.
Solution Approach 2:
The lid wafer is designed to perform multiple functions simultaneously: it provides mechanical protection, maintains vacuum sealing, contributes to thermal isolation through its frame structure, and enables precise distance control. This multi-functionality reduces the number of separate components needed and simplifies the overall manufacturing process.
2Reliability
If equal-sized lid and substrate wafers are used, then proper sealing is achieved, but material flexibility and cost efficiency decrease
Solution Approach 1:
The patent employs asymmetric wafer sizing where the lid wafer is smaller than the substrate wafer. The frame structure compensates for this asymmetry by extending to provide proper sealing and mechanical support. This asymmetric design allows selection of optimal materials for each wafer based on their specific functional requirements rather than being constrained by size matching.
Solution Approach 2:
The sealing function is segmented from the wafer size constraint. The frame structure is designed to extend beyond the lid wafer edges to provide sealing contact with the substrate, allowing the lid wafer itself to be smaller while maintaining effective sealing through the distributed frame structure.
3Measurement precision
If the membrane is thermally isolated from the substrate, then measurement sensitivity improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces a frame structure as an intermediary element between the membrane and substrate that provides thermal isolation. This frame acts as a thermal barrier while maintaining mechanical support, achieving thermal isolation through a dedicated structural element rather than relying on precise positioning alone.
Solution Approach 2:
The thermal isolation is achieved not only through vertical distance control but also through the horizontal extension of the frame structure. The frame creates a three-dimensional thermal barrier that combines vertical spacing with horizontal coverage, providing robust thermal isolation that is less sensitive to manufacturing variations in a single dimension.
4Productivity
If wafer-level packaging is implemented, then productivity increases, but device complexity increases
Solution Approach 1:
The patent merges multiple packaging operations into a single wafer-level process. The substrate and lid wafer are processed, aligned, and bonded together in one integrated sequence at the wafer level rather than processing individual devices separately. This consolidation dramatically improves productivity while the standardized frame design keeps process complexity manageable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces costs and complexity by allowing for precise control over the distance between substrates, enabling efficient encapsulation of sensitive sensors like bolometers, and allows for the use of different substrate materials, improving yield and flexibility in manufacturing, while maintaining the sensitivity of infrared sensors and micromechanical devices.
Implementation Method 1
A method involving the use of a frame with a layer sequence of copper and tin for solid liquid interdiffusion (SLID) to connect substrates
Implementation Method 2
a first frame and a second frame which are adjacently arranged, which adjoin one another along a boundary area, the boundary area including an alloy of the first metal and a second metal
Implementation Method 3
the connection is made in a vacuum to create a self-contained volume
Data Source
AI summary
A package including an electrical circuit may be produced in a more efficient manner when on a substrate including a plurality of electrical circuits the circuits are tested for their functionality and when the functional circuits are connected, by means of a frame enclosing the circuit on the surface of the substrate, to a second substrate whose surface area is smaller than that of the first substrate. The substrates are connected, by means of a second frame, which is adapted to the first frame and is located on the surface of the second substrate, such that the first and second frames lie one on top of the other. Subsequently, the functional packaged circuits may be singulated in a technologically simple manner.