Hardware Coprocessor Engine for Parallel Computer Vision Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional general-purpose programmable processors are inefficient in exploiting parallelism and optimizing data paths for computer vision processing, leading to suboptimal performance and inflexibility in handling new tasks due to inherent data and control dependencies.
Innovation Solution
Implementing a hardware coprocessor engine that executes directed acyclic graphs (DAGs) for computer vision tasks, allowing for parallel operation on variable-size multidimensional vectors and optimizing memory bandwidth, thereby eliminating control flow dependencies and expressing full parallelism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional general-purpose programmable processors are used to execute sequential instruction streams, then the processors can handle diverse problem domains with flexible programming, but the processors cannot efficiently exploit parallelism due to inherent data and control dependencies
Solution Approach 1:
The patent segments the processing architecture by introducing multiple independent data paths (first data path, second data path, etc.) that can operate simultaneously. Each data path is equipped with its own set of operators (addition, subtraction, multiplication, division) and can process different data streams in parallel, thereby resolving the contradiction between versatility and parallelism exploitation efficiency
Solution Approach 2:
The patent transitions from sequential single-instruction processing to a multi-dimensional parallel processing model where multiple data paths operate concurrently. This dimensional expansion allows the system to maintain programming flexibility while simultaneously exploiting parallelism across multiple execution streams, effectively resolving the identified contradiction
2Productivity
If aggressive pipelining and out-of-order execution are applied to extract parallelism from instruction streams, then some parallelism can be achieved, but the gains are limited by inherent data and control dependencies
Solution Approach 1:
The patent extracts the dependency constraints from the instruction stream by dedicating separate data paths for different computational streams. This isolation removes the need for complex out-of-order execution logic and dependency checking, as each data path can execute its assigned operations independently without interfering with others, thereby improving productivity while managing complexity
Solution Approach 2:
The patent creates multiple copies of the computational infrastructure (data paths with operators) that can execute simultaneously. By copying the essential processing units rather than relying on a single complex control unit to manage dependencies, the system achieves higher parallelism productivity with reduced control complexity
3Productivity
If SIMD instructions and multiple cores are used to improve performance, then parallel processing capability increases, but the implementations become inefficient and do not exploit detailed understandings of the problem domain to optimize data paths
Solution Approach 1:
The patent applies local quality by customizing each data path for specific computational tasks. Instead of using generic SIMD units that process all data uniformly, the system creates specialized data paths with operators optimized for particular operations (addition, subtraction, multiplication, division), thereby achieving both high parallel processing performance and implementation efficiency through task-specific optimization
4Productivity
If specialized engines are implemented for computer vision tasks to achieve power and cost efficiency, then performance improves for specific tasks, but the engines are not flexible to support new or enhanced tasks
Solution Approach 1:
The patent implements universality by designing data paths that can execute multiple types of operators (addition, subtraction, multiplication, division) through a unified architecture. Each data path is configured to handle various computational operations required for different computer vision tasks, allowing the system to maintain high performance for current tasks while remaining adaptable to new and enhanced tasks through reconfiguration rather than requiring dedicated specialized engines
Data Source
AI summary
An apparatus includes a memory and a processor. The memory may be configured to store a directed acyclic graph. The processor may be configured to (i) receive a command to run the directed acyclic graph, (ii) parse the directed acyclic graph into a data flow including one or more operators, (iii) schedule the operators in one or more data paths, and (iv) generate one or more output vectors by processing one or more input vectors in the data paths. The processor generally comprises a plurality of hardware engines. The data paths may be implemented with the hardware engines. The hardware engines may operate in parallel to each other.