Package Substrate Core Capacitor Layout for Larger Capacitance
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Solution Overview
Problem
Existing electronic packaging solutions require significant area and expensive materials for capacitors, which hinders conductive routing and complicates access due to capacitors being integrated into buildup layers with leads on different levels.
Innovation Solution
Embedding capacitors within the core of the package substrate between sub-core layers, using recesses or spacers, and employing hybrid bonding for cost-effective materials and seamless integration, allowing for larger capacitors without the need for expensive dielectric materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If capacitors are integrated into the buildup layers of the package substrate, then capacitance is provided, but significant area is consumed and conductive routing space is reduced
Solution Approach 1:
The patent moves the capacitor integration from the buildup layers (horizontal plane) to the core layers (vertical integration between sub-cores). This dimensional shift allows capacitors to be formed at the interface between first and second core layers, utilizing the vertical stacking dimension rather than consuming horizontal substrate area. The capacitor structure spans across the interface of two sub-cores, effectively using the third dimension (height/layer stacking) to provide capacitance without reducing the planar area available for conductive routing.
2Quantity of substance
If capacitors are integrated into the buildup layers, then capacitance is provided, but manufacturing cost increases due to expensive materials and processing
Solution Approach 1:
The patent combines the capacitor formation process with the existing core layer stacking and bonding process. By forming capacitors at the interface between sub-cores during the same manufacturing sequence, the patent eliminates separate capacitor fabrication steps. The capacitor electrodes are formed using the same conductive material layers that are already being deposited for interconnect purposes, and the dielectric layer is formed as part of the core layer structure. This merging of processes reduces manufacturing complexity and cost.
Solution Approach 2:
The core layer interface structure serves multiple functions: it provides mechanical bonding between sub-cores, electrical interconnection through vias, and capacitance through the embedded capacitor structure. The dielectric layer at the core interface serves both as electrical insulation for the bonding process and as the capacitor dielectric. This multi-functionality eliminates the need for separate capacitor-specific materials and processes, reducing overall manufacturing cost.
3Quantity of substance
If capacitors are integrated into buildup layers with leads at different levels, then capacitance is provided, but access to capacitor structure becomes difficult
Solution Approach 1:
Instead of having capacitor leads emerge from different levels of the buildup layers (making access difficult), the patent inverts the approach by providing both capacitor electrodes through the same surface of the package substrate. The first electrode is accessed through a via in the first sub-core, and the second electrode is accessed through a via in the second sub-core, but both vias exit through the same top surface. This inversion of the lead arrangement simplifies access and testing operations.
Data Source
AI summary
Embodiments disclosed herein include a core for a package substrate. In an embodiment, the core comprises a first substrate with a first surface and a second surface, a first recess into the first surface of the first substrate, a first layer in the first recess, where the first layer is electrically conductive, a second layer over the first layer, where the second layer is a dielectric layer, and a third layer over the second layer, where the third layer is electrically conductive. In an embodiment, the core further comprises a second substrate with a third surface and a fourth surface, where the third surface of the second substrate faces the first surface of the first substrate, a second recess in the third surface of the second substrate, and a fourth layer in the second recess, where the fourth layer is electrically conductive, and the fourth layer contacts the third layer.