Core Partition Scan Circuit for Independent Internal and Port Testing
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Solution Overview
Problem
Conventional testing device designs face increased complexity and inconvenience due to the need for the upper level partition circuit to change in response to changes in the structure of the wrapper chains of the core partition circuit, making it difficult to efficiently manage circuit design.
Innovation Solution
A core partition circuit and testing device are designed with a decompression circuit, switching circuits, and compression circuits, where the wrapper scanning circuit is configured between the decompression and compression circuits, allowing independent operation in internal and external test modes without requiring changes to the upper level compression logic circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the wrapper scanning circuit is connected to the upper level compression logic circuit in external test mode, then the testing device can perform external testing, but the design complexity increases and the upper level compression circuit must change when the wrapper chain structure changes
Solution Approach 1:
The patent segments the testing device into independent core partition circuits, each with its own wrapper scanning circuit and compression circuit. This segmentation allows each core partition to operate independently in external test mode without requiring changes to the upper level compression logic circuit, thereby reducing design complexity while maintaining external test capability.
Solution Approach 2:
The patent designs the core partition circuit with a universal structure that can function in both internal test mode and external test mode. The wrapper scanning circuit is configured to scan both internal logic and port logic, and the compression circuit can compress both internal logic and port logic, eliminating the need for different circuit designs for different test modes.
2Adaptability or versatility
If the upper level compression logic circuit is designed to accommodate changes in wrapper chain structure, then the testing device can adapt to different core partition configurations, but the design convenience decreases
Solution Approach 1:
By segmenting the testing device into independent core partition circuits with self-contained compression circuits, the patent eliminates the need for the upper level compression logic circuit to adapt to wrapper chain structure changes. Each core partition stands alone, making the overall design more convenient while maintaining configuration adaptability.
Solution Approach 2:
Each core partition circuit is designed to be self-sufficient with its own compression circuit that can independently compress both internal logic and port logic. This self-service capability removes the burden from the upper level compression logic circuit, improving design convenience while preserving the ability to adapt to different configurations.
3Productivity
If the wrapper scanning circuit structure changes, then the testing device can be optimized for different testing needs, but the upper level compression logic circuit must be redesigned
Solution Approach 1:
The patent segments the compression functionality into individual core partition circuits, each with its own compression circuit. This allows the wrapper scanning circuit structure to be changed or optimized without affecting the upper level compression logic circuit, as each core partition operates independently. This segmentation eliminates redesign time while maintaining testing optimization flexibility.
Solution Approach 2:
The core partition circuit is designed with universal compression capability that can handle both internal logic and port logic regardless of the wrapper scanning circuit structure. This universality allows the wrapper scanning circuit to be optimized for different testing needs without requiring changes to the compression logic, saving redesign time.
Data Source
AI summary
A core partition circuit comprises a first decompression circuit, a second decompression circuit, a first switching circuit, an wrapper scanning circuit, a first compression circuit, a second compression circuit and a second switching circuit. The first and second decompression circuits decompress an input signal. The first switching circuit outputs the output signal of the first decompression circuit or the second decompression circuit according to a first control signal. The wrapper scanning circuit receives the output signal of the first decompression circuit or the second decompression circuit to scan the internal or the port of the core partition circuit. The first and second compression circuits respectively compress the internal logic and the port logic of the core partition circuit. The second switching circuit outputs the compressed internal logic or port logic of the core partition circuit according to the first control signal.