Core-Shell Fin Structure for Lower Capacitance Semiconductor Gates
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating hybrid fin structures with high-k dielectric materials, which lead to defects and increased cell capacitance as devices scale down, limiting device performance.
Innovation Solution
Implementing a core-shell structured top portion with a low-k dielectric material core and a high-k dielectric material shell, which provides improved etch resistance and reduced cell capacitance, allowing for continued scaling while maintaining device characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If high-k dielectric material is used in the bulk top portion to provide etching resistance, then etching resistance is improved, but device capacitance increases and fabrication defects occur
Solution Approach 1:
The top portion is segmented into two distinct layers: a low-k dielectric material layer (first dielectric material) and a high-k dielectric material layer (second dielectric material). This segmentation allows each layer to perform its specialized function - the low-k layer reduces capacitance while the high-k layer provides etching resistance, resolving the contradiction between these two opposing requirements.
Solution Approach 2:
The invention uses a composite structure combining two different dielectric materials with complementary properties. The low-k dielectric material (e.g., silicon oxide) provides low capacitance, while the high-k dielectric material (e.g., hafnium oxide) provides high etching resistance. This composite approach allows the device to simultaneously achieve both low capacitance and high etching resistance.
2Strength
If high-k dielectric material is used in the bulk top portion, then etching resistance is improved, but fabrication defects increase
Solution Approach 1:
By segmenting the top portion into separate low-k and high-k dielectric layers, the invention isolates the high-k material to specific regions where etching resistance is needed, while using low-k material in regions where fabrication defects are a concern. This reduces overall defect rates while maintaining necessary etching resistance.
Solution Approach 2:
The invention applies different dielectric materials to different locations within the top portion based on functional requirements. The high-k dielectric material is applied locally where etching resistance is critical, while low-k dielectric material is used in other areas to minimize defects and capacitance, achieving local optimization of material properties.
3Productivity
If device scaling continues, then production efficiency and cost reduction are improved, but fabrication of bulk top portion becomes increasingly challenging
Solution Approach 1:
The segmented structure of separate low-k and high-k dielectric layers can be formed using standard semiconductor fabrication techniques such as selective deposition and etching. This modular approach simplifies the manufacturing process compared to attempting to fabricate a uniform bulk high-k structure at scaled dimensions, making continued scaling more manageable.
Solution Approach 2:
The invention changes the material parameters (dielectric constant k) at different locations within the top portion to optimize device performance at scaled dimensions. By using low-k material to reduce capacitance and high-k material to provide etching resistance, the device can be scaled down while maintaining electrical characteristics and reducing the complexity of fabrication.
Data Source
AI summary
A method includes forming a first fin structure and a second fin structure protruding from a substrate, forming a dielectric fin between the first fin structure and the second fin structure, recessing the dielectric fin to form a trench between the first fin structure and the second fin structure, and depositing a first dielectric layer on sidewall surfaces of the trench and on a top surface of the recessed dielectric fin. After the depositing the first dielectric layer, a second dielectric layer is deposited in the trench. The method further includes depositing a third dielectric layer to cap the second dielectric layer in the trench, and forming a gate structure on the first fin structure, the second fin structure, and the third dielectric layer.