Coreless Interposer Substrate Fabrication via Recessed Grooves
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional interposer substrate fabrication methods are complex, costly, and limited by thickness and line width/line space constraints, leading to reduced electrical performance and increased package thickness, which hinders the achievement of low-profile and compact-size requirements in semiconductor packages.
Innovation Solution
A method involving the formation of recessed grooves on a carrier with dielectric material layers and conductive blocks, eliminating the need for an insulating layer and additional conductive layers, allowing for a coreless interposer substrate with fine pitches and reduced fabrication complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional interposer substrate fabrication methods are used, then electrical connection is achieved, but the fabrication process becomes complex and costly
Solution Approach 1:
The patent extracts and removes the insulating layer from the traditional interposer substrate structure, retaining only the essential conductive blocks and wiring layers on the carrier substrate. This simplification maintains electrical connection functionality while eliminating unnecessary fabrication steps and reducing overall complexity of the fabrication process
Solution Approach 2:
The method discards the insulating layer material that would normally be present between conductive elements, directly forming conductive blocks and wiring layers on the carrier. This discarding approach eliminates the need for additional insulating layer fabrication steps, reducing process complexity and cost while maintaining electrical performance
2Reliability
If additional conductive layers are added to improve electrical performance, then electrical connection is enhanced, but fabrication cost increases
Solution Approach 1:
The patent extracts unnecessary additional conductive layers from the traditional design, using only the essential conductive blocks and wiring layers directly formed on the carrier substrate. This reduction in layer count maintains adequate electrical performance while significantly reducing fabrication cost and process complexity
3Length of stationary object
If the interposer substrate thickness is reduced to meet low-profile requirements, then compact size is achieved, but fabrication difficulty increases
Solution Approach 1:
By removing the insulating layer and reducing the number of conductive layers, the patent achieves a thinner interposer substrate structure. This extracted simplified structure reduces overall thickness to meet low-profile requirements while actually decreasing fabrication difficulty by eliminating steps for creating and patterning multiple thin insulating and conductive layers
Solution Approach 2:
Instead of building up multiple thin layers that are difficult to fabricate, the patent inverts the approach by using a carrier substrate with directly formed conductive blocks and wiring layers. This inverted construction method achieves thin profile while simplifying fabrication, as the conductive features are formed directly on the carrier without requiring precise alignment of multiple thin layers
4Productivity
If line width and line space are reduced to increase I/O number, then density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from planar wiring patterns constrained by line width/line space to a three-dimensional arrangement using conductive blocks that can be vertically positioned and connected. This dimensional change allows increased I/O density without requiring progressively smaller line widths, as connections can be established through vertical vias and stacked conductive blocks rather than only through planar routing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process, reduces costs, and addresses design limitations due to line width/line space constraints, enabling the creation of interposer substrates that meet low-profile and compact-size requirements without compromising electrical performance.
Implementation Method 1
forming a first dielectric material layer in the recessed grooves
Implementation Method 2
An electroplating process is performed to form in the openings of the resist layer 24 a conductive material that is electrically connected with the second wiring layer 21b
Data Source
AI summary
The invention provides an interposer substrate and a method of fabricating the same. The method includes: etching a carrier to form a recessed groove thereon; filling a dielectric material in the recessed groove to form a first dielectric material layer, or forming a patterned first dielectric material layer on the carrier; forming a first wiring layer, a first conductive block and a second dielectric material layer on the carrier and the first dielectric material layer sequentially, with the first wiring layer and the first conductive block embedded in the second dielectric material layer; and forming a second wiring layer and a second conductive block on the second dielectric material layer. A coreless interposer substrate having fine pitches is thus fabricated.