Coreless Package on Package Substrate for Thinner IC Stacks
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Solution Overview
Problem
The increasing demand for smaller, higher performance Package on Package (PoP) structures in integrated circuit devices is hindered by the limitations of conventional signal routing, which results in longer signal paths leading to IR drops and slower systems, particularly in portable applications where thinner packages are required.
Innovation Solution
The implementation of coreless substrates and innovative connector arrangements, such as copper columns and flip chip mounting, reduces the thickness and length of signal paths, enabling shorter signal routing and lower IR drops, thereby enhancing performance and form factor in PoP structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional PoP structures with core substrates are used, then structural support and connectivity are provided, but the package thickness becomes greater than 1 millimeter and signal paths become longer
Solution Approach 1:
The patent removes the core substrate from the PoP structure, eliminating the thick central support layer that traditionally provided mechanical strength and routing. This extraction of the core element enables the package thickness to be reduced below 1 millimeter while maintaining necessary structural support through alternative means such as substrate frames or edge-only support structures.
Solution Approach 2:
The patent transitions from conventional two-dimensional planar routing to three-dimensional vertical routing by positioning connectors at the periphery and using vias to route signals through the vertical dimension. This dimensional change allows signal paths to be shortened despite the reduced package thickness, as signals can travel vertically through vias rather than laterally through thick substrate cores.
2Reliability
If conventional signal routing through substrates is used, then connections are established, but IR drops increase and system performance decreases
Solution Approach 1:
By removing the thick core substrate, the patent eliminates the primary source of long signal paths that caused significant IR drops. The shortened signal paths in the coreless structure reduce resistance and improve electrical performance, directly addressing the energy loss issue.
Solution Approach 2:
The patent implements vertical signal routing through vias that travel perpendicular to the substrate planes, creating shorter electrical paths compared to traditional lateral routing through the substrate core. This three-dimensional routing approach reduces the length of current paths, thereby minimizing IR drops and improving power efficiency.
3Length of moving object
If thinner packages are implemented, then portability is improved, but manufacturing complexity increases
Solution Approach 1:
The removal of the core substrate simplifies the manufacturing process by eliminating complex core drilling, plating, and lamination steps associated with traditional multi-layer substrates. The coreless structure can be manufactured using simpler substrate frame techniques and direct via formation, reducing manufacturing complexity despite the thinner profile.
Data Source
AI summary
Methods and apparatus for thinner package on package (“PoP”) structures. A structure includes a first integrated circuit package including at least one integrated circuit device mounted on a first substrate and a plurality of package on package connectors extending from a bottom surface; and a second integrated circuit package including at least another integrated circuit device mounted on a second substrate and a plurality of lands on an upper surface coupled to the plurality of package on package connectors, and a plurality of external connectors extending from a bottom surface; wherein at least the second substrate is formed of a plurality of layers of laminated dielectric and conductors. In another embodiment a cavity is formed on the bottom surface of the first substrate and a portion of the another integrated circuit extends partially into the cavity. Methods for making the PoP structures are disclosed.