Coreless Substrate Pillar Formation via Seed Layer Plating

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Solution Overview

Problem

There is a need for a robust and efficient process to manufacture ultra-thin substrates with pillars for component carriers, which require a reliable electrical connection and minimal investment costs, while maintaining flexibility and mechanical support.

Innovation Solution

A component carrier is created with a stack of electrically conductive and insulating layers, featuring pillars with a seed layer and a second plating structure, allowing for a coreless design and efficient manufacturing process that eliminates the need for additional metallization steps, enabling a robust and flexible connection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If traditional substrate manufacturing processes are used, then mechanical support is provided, but the substrate thickness cannot be reduced to ultra-thin dimensions

Engineering Contradiction:
Improvesubstrate thicknessVSAvoidmechanical support
Core Design Contradiction:
Length of moving objectVSStrength

Solution Approach 1:

The patent removes the traditional substrate core entirely, extracting only the essential functions of electrical connectivity and mechanical support. The coreless design eliminates the substrate thickness constraint while maintaining structural integrity through the layer stack and pillar architecture.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The component carrier is segmented into discrete functional layers (conductive layers, insulating layers, pillars) that can be independently formed and stacked. This segmentation allows ultra-thin dimensions while maintaining mechanical support through the distributed layer structure rather than a continuous substrate.

Inventive Principle:
Principle #1Segmentation

2Reliability

If additional metallization steps are added to form pillars, then electrical connection reliability is improved, but manufacturing complexity and investment costs increase

Engineering Contradiction:
Improveelectrical connectionVSAvoidmanufacturing process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the pillar formation process with the existing copper layer deposition process. The pillars are formed by selectively removing dielectric material to expose copper that was already deposited, eliminating the need for separate metallization steps and reducing manufacturing complexity while maintaining electrical connection reliability.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

Copper layers are deposited in advance during the standard lamination process, before the final pillar formation step. This preliminary action ensures that the metallization is already in place, requiring only selective exposure through dielectric removal rather than additional metallization steps.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If pillars are formed on a substrate, then electrical connectivity is achieved, but the manufacturing process becomes lengthy and costly

Engineering Contradiction:
Improveelectrical connectivityVSAvoidmanufacturing cycle time
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The copper conductive layers are formed in advance during the standard substrate lamination process, before the coreless pillar formation steps. This preliminary metallization allows pillars to be created simply by exposing the pre-formed copper, significantly reducing the manufacturing cycle time while ensuring reliable electrical connectivity.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution provides a short process flow, reduced investment costs, and a robust connection for the pillar process, enabling flexible application of coreless pillar technology, while maintaining mechanical support and electrical connectivity for ultra-thin substrates.

Implementation Method 1

a pillar which includes a seed layer portion on the first plating structure and a second plating structure on the seed layer portion

Methodology Applied
Scientific EffectElectroplating: Electroplating

Data Source

PatentUS11553599B2Component carrier comprising pillars on a coreless substrate
Publication Date: 2023.01.10 AT&S (CHONGQING) CO LTD
  • US11553599B2 patent drawing
  • US11553599B2 patent drawing
  • US11553599B2 patent drawing

AI summary

A component carrier includes a stack with an electrically conductive layer structure and an electrically insulating layer structure. The electrically conductive layer structure having a first plating structure and a pillar. The pillar has a seed layer portion on the first plating structure and a second plating structure on the seed layer portion. A method of manufacturing such a component carrier and an arrangement including such a component carrier are also disclosed.