Coreless Substrate High Density Layout Manufacturing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional substrate manufacturing methods involve core substrates with low layout density and high manufacturing costs due to complex procedures like drilling, plating, and layout forming.
Innovation Solution
A coreless substrate is developed with a first dielectric layer, embedded circuit, pads, and solder masks, where the core is eliminated by using a carrier and conductive layers, allowing for high-density layout and reduced thickness with lower manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a core substrate is used in conventional substrate manufacturing, then the substrate structure is stable and easy to manufacture, but the layout density is low and the manufacturing cost is high
Solution Approach 1:
The patent removes the core substrate from the traditional PCB structure, extracting only the essential function of providing mechanical support and electrical connectivity. This is achieved by using a thin dielectric layer without a core, allowing circuits to be formed directly on the substrate surface, thereby increasing layout density while maintaining manufacturing simplicity through a streamlined process.
Solution Approach 2:
The invention transitions from a traditional multi-layer core substrate structure to a planar surface-mounted circuit approach. By eliminating the vertical core layer and forming circuits on the surface of a thin dielectric layer, the patent enables higher layout density in the horizontal plane while reducing overall substrate thickness and complexity.
2Reliability
If drilling, plating, and layout forming procedures are used in conventional substrate manufacturing, then the substrate structure is robust, but the manufacturing procedure is complicated and cost is high
Solution Approach 1:
The patent eliminates the core substrate component entirely, removing the need for drilling and plating operations associated with through-holes. The manufacturing process is simplified to forming circuits directly on the surface of a thin dielectric layer, reducing procedural complexity while maintaining structural reliability through the embedded circuit design.
Solution Approach 2:
The invention uses a thin dielectric layer without a permanent core substrate, effectively replacing the robust but complex core structure with a simpler, thinner alternative. This approach reduces manufacturing steps and costs while achieving the necessary structural integrity for the application.
3Strength
If a core substrate with certain thickness is used, then the substrate provides mechanical strength, but the product thickness is increased and layout density is reduced
Solution Approach 1:
The patent removes the thick core substrate and replaces it with a thin dielectric layer that provides sufficient mechanical support for surface-mounted circuits. This extraction of the core component reduces substrate thickness while maintaining adequate strength through the alternative structure of embedded circuits within the thin dielectric layer.
Solution Approach 2:
The invention employs a thin dielectric layer as a flexible substrate alternative to rigid core substrates. This thin film structure provides the necessary mechanical properties while enabling reduced overall thickness and higher layout density, effectively replacing the traditional thick core with a thinner, more flexible structure.
Data Source
AI summary
The present invention relates to a coreless substrate and a method for making the same. The method for making the coreless substrate includes: (a) providing a carrier and a first conductive layer, wherein the carrier has a first surface and a second surface, and the first conductive layer is disposed on the first surface of the carrier; (b) forming a first embedded circuit on the first conductive layer; (c) forming a first dielectric layer so as to cover the first embedded circuit; (d) removing the carrier; (e) removing part of the first conductive layer so as to form at least one first pad; and (f) forming a first solder mask so as to cover the first embedded circuit and the first dielectric layer and to expose the first pad. Therefore, the coreless substrate of the present invention has high density of layout and involves low manufacturing cost.