Core-less IC Substrate Symmetrical Laminate Fabrication
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Solution Overview
Problem
Existing core-less substrates for integrated circuits face challenges such as high manufacturing costs, reduced yield, substrate warping, and poor thermal and electrical performance due to the use of expensive thin film interconnects and metal stiffeners, which are not suitable for miniaturization and high-performance applications.
Innovation Solution
A novel manufacturing technique for multilayer interconnect support structures using a symmetrical layup of alternating conductive and insulating layers with solid copper vias, fabricated through a process involving etchant resistant barrier layers, photoresist coating, and hot press lamination, resulting in a self-supported, flat, and cost-effective substrate with high reliability and planarity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If expensive thin film interconnects and metal stiffeners are used in core-less substrates, then substrate strength and flatness are improved, but manufacturing cost increases and yield decreases
Solution Approach 1:
The patent changes the material parameters from expensive thin films to cost-effective laminated composite materials, achieving comparable mechanical strength through optimized layer composition and thickness while reducing manufacturing cost
Solution Approach 2:
The patent employs composite laminated structures combining organic and inorganic layers with different mechanical properties, where the composite action provides sufficient substrate strength and flatness without requiring expensive metal stiffeners
2Length of stationary object
If thin film interconnects are used in core-less substrates, then substrate thickness is reduced, but thermal and electrical performance deteriorate
Solution Approach 1:
The patent uses composite laminated materials with optimized thermal and electrical properties, where specific layers are designed to conduct heat and electricity effectively while maintaining thin overall substrate thickness
Solution Approach 2:
The patent applies different material properties to different regions and layers of the substrate, with conductive layers optimized for electrical performance and thermally conductive layers for heat dissipation, achieving high reliability in a thin profile
3Device complexity
If asymmetric substrate structures are fabricated, then manufacturing process is simplified, but substrate warping occurs
Solution Approach 1:
The patent deliberately designs a symmetric laminated structure with balanced organic and inorganic layers on both sides of the substrate, which compensates for differential stress and prevents warping during fabrication and operation
Solution Approach 2:
The patent optimizes the thickness and material properties of each layer in the symmetric laminate to achieve stress balance, maintaining substrate flatness while using a manufacturable lamination process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The technique achieves a high-performance, thin, and flat core-less laminated substrate with multiple conductive layers, minimizing thermal impedance and electrical signal loss, suitable for large-scale manufacture and various IC assembly formats, including Flip Chip and Wire Bond processes.
Implementation Method 1
depositing a first etchant resistant barrier layer onto said first base layer
Implementation Method 2
applying a protective coating of photoresist to said second base layer
Implementation Method 3
hot press lamination
Data Source
AI summary
A method of fabricating an electronic substrate comprising the steps of; (A) selecting a first base layer; (B) depositing a first etchant resistant barrier layer onto the first base layer; (C) building up a first half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers; (D) applying a second base layer onto the first half stack; (F) applying a protective coating of photoresist to the second base layer; (F) etching away the first base layer; (G) removing the protective coating of photoresist; (H) removing the first etchant resistant barrier layer; (I) building up a second half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers, wherein the second half stack has a substantially symmetrical lay up to the first half stack; (J) applying an insulating layer onto the second hall stack of alternating conductive layers and insulating layers, (K) removing the second base layer, and (L) terminating the substrate by exposing ends of vias on outer surfaces of the stack and applying terminations thereto.