Semiconductor Package Corner Post Layout for Delamination Relief
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The delamination between the seed layer and the post-passivation layer, as well as between the seed layer and the conductive pads, is exacerbated at the corners of integrated circuits due to stress concentration during thermal processes, which compromises the reliability and performance of the circuits.
Innovation Solution
The openings of the post-passivation layer in the corner regions are shifted towards the center of the integrated circuit, reducing stress concentration and enhancing the alignment and uniformity of the seed layer and conductive posts, thereby alleviating delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the openings of the post-passivation layer are aligned with the corners of the integrated circuit, then the manufacturing process is simplified, but stress concentration occurs at the corners causing delamination between the seed layer and the post-passivation layer
Solution Approach 1:
The patent applies asymmetry by intentionally misaligning the openings in the post-passivation layer from the corner regions of the integrated circuit. Instead of symmetric alignment with corners, the openings are positioned offset from the corners, creating an asymmetric configuration that redistributes stress away from the corner regions where delamination would otherwise occur.
Solution Approach 2:
The patent applies local quality by creating different opening configurations in different regions of the post-passivation layer. Corner regions have openings that are offset from the corners, while non-corner regions maintain standard alignment. This localized modification addresses stress concentration specifically at corners without affecting the overall manufacturing process or other regions of the circuit.
2Productivity
If the openings are positioned at the corners for easy manufacturing, then production efficiency is improved, but stress concentration during thermal processes compromises circuit reliability
Solution Approach 1:
The patent applies local quality by creating different opening configurations in different regions of the post-passivation layer. Corner regions have openings that are offset from the corners, while non-corner regions maintain standard alignment. This localized modification addresses stress concentration specifically at corners without affecting the overall manufacturing process or other regions of the circuit.
Solution Approach 2:
The patent applies partial action by modifying only the opening positions in corner regions while leaving the rest of the structure unchanged. This selective modification addresses the specific problem of corner stress concentration without requiring complete redesign of the entire manufacturing process, thus maintaining production efficiency while improving reliability.
3Device complexity
If standard alignment is used for all openings, then manufacturing complexity is reduced, but delamination occurs between the seed layer and conductive pads at corner regions
Solution Approach 1:
The patent applies local quality by creating different opening configurations in different regions of the post-passivation layer. Corner regions have openings that are offset from the corners, while non-corner regions maintain standard alignment. This localized modification addresses stress concentration specifically at corners without affecting the overall manufacturing process or other regions of the circuit.
Solution Approach 2:
The patent applies asymmetry by intentionally misaligning the openings in the post-passivation layer from the corner regions of the integrated circuit. Instead of symmetric alignment with corners, the openings are positioned offset from the corners, creating an asymmetric configuration that redistributes stress away from the corner regions where delamination would otherwise occur.
Data Source
AI summary
An integrated circuit has corner regions and non-corner regions between the corner regions and includes a semiconductor substrate, conductive pads, passivation layer, post-passivation layer, first conductive posts, and second conductive posts. The conductive pads are disposed over the semiconductor substrate. The passivation layer and the post-passivation layer are sequentially disposed over the conductive pads. The first conductive posts and the second conductive posts are disposed on the post-passivation layer and are electrically connected to the conductive pads. The first conductive posts are disposed in the corner regions and the second conductive posts are disposed in the non-corner regions. Each of the first conductive posts has a body portion and a protruding portion connected to the body portion. A central axis of the body portion of the first conductive post has an offset from a central axis of the protruding portion of the first conductive post.


