Corrective Memory Program Verify Using Reduced Vpass(PV)
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Solution Overview
Problem
Existing corrective program verify operations in memory devices suffer from read window budget (RWB) degradation due to cell-to-cell interference and lateral charge migration, leading to increased errors and data retention loss, without effectively addressing these issues without additional programming time or circuitry area consumption.
Innovation Solution
Implementing a corrective program verify operation with a program verify pass through voltage (Vpass(pv)) that is lower than the read operation voltage (Vpass(read)) by an offset amount (PV offset) for adjacent wordlines, adjusted based on the target programming level and interference/lateral charge migration loss levels, to shift threshold voltage placement and reduce RWB loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a standard program verify operation is performed with normal pass through voltage, then the verify operation can be completed, but read window budget degradation occurs due to cell-to-cell interference and lateral charge migration
Solution Approach 1:
The patent applies a reduced pass through voltage (Vpass(pv) = Vpass(read) - PV offset) during program verify operations compared to normal read operations. This parameter change in voltage level reduces the strength of electric field interference on adjacent wordlines, thereby minimizing cell-to-cell interference and lateral charge migration while still enabling effective verify operations. The PV offset is determined based on target programming level and interference loss levels to optimize the balance between verify effectiveness and RWB preservation.
2Object-affected harmful factors
If higher pass through voltage is applied to adjacent wordlines during program verify, then cell-to-cell interference is reduced, but lateral charge migration increases causing more data retention loss
Solution Approach 1:
The patent implements a reduced pass through voltage level (Vpass(pv) = Vpass(read) - PV offset) specifically for program verify operations. This parameter change creates an optimal balance where the voltage is sufficiently high to maintain wordline selection integrity and reduce cell-to-cell interference, but low enough to minimize lateral charge migration to adjacent wordlines, thereby preserving data retention without compromising verify effectiveness.
3Reliability
If corrective measures are applied to address read window budget loss, then data retention improves, but programming time increases
Solution Approach 1:
The patent determines and applies an appropriate PV offset based on target programming level and interference loss levels before executing the program verify operation. This preliminary configuration of the reduced pass through voltage ensures that the verify operation is performed with optimal voltage settings from the start, preventing RWB degradation before it occurs rather than requiring corrective actions afterward, thereby maintaining programming speed while improving data retention.
4Manufacturing precision
If additional circuitry is added to compensate for lateral charge migration, then read window budget is preserved, but device complexity increases
Solution Approach 1:
The patent preserves read window budget by changing the voltage parameter (applying reduced Vpass(pv) during program verify) rather than adding corrective circuitry. This parameter-based solution achieves RWB preservation through voltage level adjustment controlled by existing control logic, avoiding the need for additional hardware components and maintaining device simplicity while effectively addressing lateral charge migration and cell-to-cell interference.
Data Source
AI summary
A program operation is initiated to program a set of target memory cells of a target wordline of a memory device to a target programming level. During a program verify operation of the program operation, a program verify voltage level is caused to be applied to the target wordline to verify programming of the set of target memory cells. A pass through read voltage level associated with the target wordline is identified. During the program verify operation, a pass through voltage level is caused to be applied to at least one of a first wordline or a second wordline, wherein the pass through read voltage level is the read voltage level reduced by an offset value.