Corrigible Comparator Circuit for Low-Delay TMR Self-Correction
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Solution Overview
Problem
Existing triple modular redundancy systems face challenges with signal propagation delay and silicon area usage in providing self-correction functions, particularly in feedback circuits for multiple redundancy modules.
Innovation Solution
A corrigible comparator is introduced, comprising a data-forwarding stage, comparison stage, and correction stage, which reduces propagation delay and silicon area by integrating the provision of a voted output binary value and feedback binary value in a single comparison stage, utilizing clock-based trigger events for forwarding and correction operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate feedback circuits are provided for each redundancy module, then self-correction functionality is achieved, but signal propagation delay increases
Solution Approach 1:
The patent combines the feedback circuit functionality into a shared comparison stage that serves multiple redundancy modules simultaneously. The comparison stage receives first comparison binary values from multiple data-forwarding stages and generates feedback binary values for correction, eliminating the need for separate feedback circuits for each module and thereby reducing signal propagation delay.
Solution Approach 2:
The comparison stage is designed to perform multiple functions: it compares first comparison binary values from different redundancy modules, generates feedback binary values for correction, and outputs voted results. This multi-functional design reduces the overall circuit complexity and signal path length compared to dedicated feedback circuits for each module.
2Reliability
If separate feedback circuits are provided for each redundancy module, then self-correction functionality is achieved, but silicon area usage increases
Solution Approach 1:
The patent merges the feedback circuit functionality into a shared comparison stage that serves multiple redundancy modules simultaneously. This consolidation reduces the total silicon area required compared to implementing separate feedback circuits for each redundancy module, as the comparison logic and feedback generation are shared resources.
Solution Approach 2:
The comparison stage is designed to perform multiple functions: it compares first comparison binary values from different redundancy modules, generates feedback binary values for correction, and outputs voted results. This multi-functional design reduces the overall circuit footprint by eliminating redundant circuitry across multiple modules.
3Ease of operation
If clock-based trigger events are used for forwarding and correction operations, then operational control is improved, but device complexity increases
Solution Approach 1:
The patent employs periodic clock-based trigger events to control the timing of data forwarding and correction operations. The clock signal periodically activates the data-forwarding stage to forward comparison values and the correction stage to apply corrections based on feedback, providing rhythmic operational control that simplifies timing management despite the added control logic.
Solution Approach 2:
The system uses feedback binary values generated by the comparison stage to control the correction stage's operation. The feedback mechanism provides operational control by automatically triggering correction actions when discrepancies are detected, improving ease of operation through automatic control while the clock-based triggering manages the overall operational rhythm.
Data Source
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AI summary
The invention is directed to a corrigible comparator (100). The comparator comprises a data-forwarding stage configured to provide in dependence on a clock-based forwarding trigger event a first comparison binary value (Ax) that is correlated to a current binary value of input binary data signal (D). In a comparison stage, this value is compared to an external second comparison binary value (Bx) and an output binary value (Qx) that is correlated to the first comparison binary value (Ax) is provided when the compared values are identical. A feedback binary value (SCx) correlated to the first comparison binary value (Ax) is provided. A correction stage (Fx) is configured to receive external feedback binary values (SCy, SCz) and, depending on a correction trigger event, to provide to the comparison stage a corrected binary value (Ax') correlated to the feedback binary values when they have the same binary value.