Cortex-M Coprocessor RNN Acceleration via MCR and CDP Instructions
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Solution Overview
Problem
Existing solutions for executing recurrent neural networks on processors face challenges of low efficiency, high cost, and inflexibility.
Innovation Solution
A method and system that utilize a Cortex-M processor to accelerate recurrent neural networks by configuring internal registers through MCR instructions and enabling basic operators like matrix multiplication, vector arithmetic, and activation functions via CDP instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If cloud-based processing is used for recurrent neural networks, then computational capability is improved, but data transmission bandwidth and timeliness deteriorate
Solution Approach 1:
The patent introduces an ARM coprocessor as an intermediary computing unit between the host processor and cloud system. The coprocessor handles RNN computations locally using dedicated instruction sets (MCR/CDP instructions), reducing the need for data transmission to cloud while maintaining computational capability for time-sensitive operations.
2Productivity
If high-performance MCU is used to handle RNN operations, then processing speed is improved, but cost deteriorates
Solution Approach 1:
The patent segments the processing system into a host processor for control and data management, and a dedicated ARM coprocessor for RNN computations. This segmentation allows the coprocessor to be optimized specifically for neural network operations with lower cost compared to using a high-performance MCU for all tasks.
Solution Approach 2:
The ARM coprocessor is designed with a universal instruction set that can handle multiple RNN operations (matrix multiplication, vector operations, activation functions) through configurable internal registers, providing multi-functional capability at lower cost than specialized hardware accelerators.
3Productivity
If dedicated hardware accelerators are designed for specific algorithms, then processing efficiency is improved, but flexibility deteriorates
Solution Approach 1:
The patent implements dynamic configurability in the ARM coprocessor through programmable internal registers that can be configured via MCR instructions. This allows the same hardware accelerator to adapt to different RNN algorithms and operations by changing register settings rather than requiring fixed hardware design, maintaining both efficiency and flexibility.
4Device complexity
If traditional processor executes RNN algorithms, then hardware complexity is reduced, but execution efficiency deteriorates
Solution Approach 1:
The patent replaces general-purpose processor instruction execution with a specialized coprocessor instruction set (MCR for register configuration, CDP for data processing). This substitution optimizes the execution path for RNN operations, improving efficiency while keeping the overall hardware architecture relatively simple through software-instruction-based optimization.
Data Source
AI summary
The application relates to a method and a system for accelerating a recurrent neural network based on a Cortex-M processor, and a medium. The method comprises: setting MCR instructions and a CDP instruction according to common basic operators of the recurrent neural network, the common basic operators comprising a matrix multiplication operator, a vector arithmetic operator, a sigmoid activation operator, a tanh activation operator and a quantization operator; configuring an internal register of a recurrent neural network coprocessor through the MCR instructions; and enabling the common basic operators of the recurrent neural network through the CDP instruction on the basis of the configured internal register.