CoWoS Interposer Fuse for Selectable Capacitance Arrays
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Solution Overview
Problem
In Chip on Wafer on Substrate (CoWoS) packaging, simultaneous switching noise (SSN) induced by current spikes in chiplets can damage circuits due to faulty capacitors in the interposer, which drain DC power and cause heating, necessitating a solution to disable faulty capacitors and utilize non-faulty ones for voltage spike drainage.
Innovation Solution
Incorporating a fuse between power and ground connections in the interposer, which can be selectively blown to disconnect faulty capacitors, allowing healthy capacitors to handle voltage spikes, thereby preventing damage and maintaining interposer functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capacitors are incorporated in the interposer to drain voltage spikes, then protection against SSN is improved, but faulty capacitors cause excessive DC power consumption and heating
Solution Approach 1:
The capacitor array is divided into individually addressable units, each with its own switch element. This segmentation allows selective activation of only the capacitors needed for SSN protection, rather than having all capacitors continuously active. The switch elements enable independent control of each capacitor segment, reducing overall DC power consumption while maintaining protection capability.
Solution Approach 2:
The capacitor array transitions from a static configuration where all capacitors are permanently connected to a dynamic configuration where capacitors can be selectively activated or deactivated. The switch elements enable this dynamic reconfiguration, allowing the system to adapt capacitor engagement based on operational needs, thereby reducing unnecessary DC power consumption and heat generation from faulty or unnecessary capacitors.
2Reliability
If capacitors are incorporated in the interposer to drain voltage spikes, then protection against SSN is improved, but faulty capacitors may heat up the interposer
Solution Approach 1:
By segmenting the capacitor array into individually controllable units with associated switch elements, the system can isolate and deactivate faulty capacitors that generate excessive heat. Each capacitor segment can be independently monitored and controlled, preventing hotspots from affecting the entire interposer structure.
Solution Approach 2:
The system incorporates monitoring circuitry that can detect faulty capacitors and automatically deactivate them through the switch elements. This self-service capability allows the interposer to identify and isolate heat-generating faulty capacitors without external intervention, maintaining thermal management and preventing overheating.
3Reliability
If a fuse is incorporated to disconnect faulty capacitors, then reliability is improved, but device complexity increases
Solution Approach 1:
The fuse function is merged with the existing switch element structure of the capacitor array. Rather than adding separate fuse components, the patent utilizes the switch elements to perform both normal operation control and fault isolation functions. This merging approach enables reliable fault disconnection while minimizing additional structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively isolates faulty capacitors, preventing damage from SSN and ensuring reliable operation by allowing only healthy capacitors to drain voltage spikes, thus enhancing the reliability and thermal management of the interposer.
Implementation Method 1
Capacitors can be incorporated in the interposer between the micro-bump connections, e.g., between a power connection and a ground connection, such that voltage spikes on the power connection is drained, e.g., transferred, to the ground through the capacitors
Implementation Method 2
Incorporating a fuse between power and ground connections in the interposer, which can be selectively blown to disconnect faulty capacitors
Data Source
AI summary
An interposer circuit includes a substrate and a dielectric layer that is disposed on top of the substrate. The interposer circuit includes two or more connection layers including a first connection layer and a second connection layer that are disposed at different depths in the dielectric layer. The interposer circuit includes a fuse that is disposed in the first connection layer. The first connection layer is coupled to a first power node and the second connection layer is coupled to a first ground node. The interposer circuit further includes a first capacitor that is in series with the fuse and is connected between the first and the second connection layers. The interposer circuit also includes first, second, and third micro-bumps on top of the dielectric layer such that the fuse is coupled between the first and second micro-bumps and the first capacitor is coupled between the second and third micro-bumps.