Tri-layer CoWoS IVR Structure for CPU Power Delivery
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Solution Overview
Problem
Central Processing Units (CPUs) face high power consumption and require stable power supply, which existing technologies struggle to efficiently manage due to the complexity of voltage regulation and layout inefficiencies in multi-tier packages.
Innovation Solution
A multi-tier package is formed using the Chip-on-Wafer-on-Substrate (CoWoS) process, where Integrated Voltage Regulator (IVR) dies are placed directly under CPU dies to minimize distance to voltage regulators, optimizing power efficiency and layout balance, and through-vias replace traditional through-molding vias to reduce manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage regulators are connected to the same CPU chip, then power supply stability is improved, but device complexity increases
Solution Approach 1:
The patent divides the voltage regulation function into separate integrated voltage regulator (IVR) dies that are bonded to the CPU die. Each IVR die is responsible for regulating voltage for specific cores or core groups, segmenting the overall voltage regulation system into modular units that can be independently designed, manufactured, and optimized.
Solution Approach 2:
The patent introduces an interposer or substrate as an intermediary component that facilitates the connection between CPU dies and IVR dies. This intermediary enables flexible routing of power and signal connections while allowing optimal placement of voltage regulators close to the cores they serve, resolving the complexity of direct integration.
2Loss of energy
If IVR dies are placed directly under CPU dies, then power efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar layout to three-dimensional multi-tier stacking, placing IVR dies directly underneath CPU dies in the vertical dimension. This vertical arrangement minimizes the current path length between voltage regulators and cores, reducing I²R losses and improving power efficiency while utilizing the third dimension to manage complexity.
Solution Approach 2:
The patent implements a nested structure where IVR dies are positioned directly under CPU dies, with each tier serving a specific function. The IVR dies are essentially nested within the vertical footprint of the CPU die, creating a compact hierarchical arrangement that optimizes electrical connectivity while maintaining manufacturability.
3Ease of manufacture
If through-vias are used instead of through-molding vias, then manufacturing cost is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent extracts the through-via formation process from the traditional through-molding approach and implements it as a separate, controlled step in the multi-tier bonding process. By forming through-vias in the IVR dies before bonding, the precision requirements are managed in a controlled fabrication environment rather than during the molding process, reducing overall manufacturing complexity.
Data Source
AI summary
A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.