CPLD-Structured ASIC Timing Preservation
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Solution Overview
Problem
High-volume markets require integrated circuits with a faster time to market and lower costs than traditional Application Specific Integrated Circuits (ASICs), which are typically slower and more expensive than Programmable Logic Devices (PLDs).
Innovation Solution
A method to port a circuit design from a Complex Programmable Logic Device (CPLD) to an Application Specific Integrated Circuit (ASIC) by selecting circuit blocks with predetermined placement information, preserving timing and reducing die size and power consumption, resulting in a structured ASIC with reduced costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ASICs are used for high-volume markets, then manufacturing precision and reliability are improved, but time to market increases and cost increases
Solution Approach 1:
The patent applies preliminary action by pre-placing circuit blocks in predetermined locations within the ASIC structure before the actual ASIC fabrication process. This pre-placement methodology, derived from PLD design tools, allows the ASIC manufacturing process to skip time-consuming placement and routing optimization steps, thereby reducing time to market while maintaining the reliability benefits of traditional ASICs.
2Manufacturing precision
If traditional ASICs are used for high-volume markets, then manufacturing precision is improved, but cost increases
Solution Approach 1:
The patent reduces manufacturing cost by performing circuit block placement in advance during the design phase using automated PLD tools, rather than during the expensive ASIC fabrication process. This preliminary placement action simplifies the ASIC manufacturing workflow, reduces design iteration costs, and enables cost-effective production while maintaining high manufacturing precision through predetermined optimal placements.
3Loss of time
If PLDs are used instead of ASICs, then time to market is reduced and cost is reduced, but manufacturing precision and reliability deteriorate
Solution Approach 1:
The patent applies copying by transferring the successful circuit block placement methodology and predetermined placement information from PLD designs to ASIC structures. Instead of using generic PLD architectures, the invention copies the optimized placement patterns and design approaches from PLDs into a fixed ASIC structure, thereby achieving PLD-like speed and cost benefits while maintaining ASIC manufacturing precision and reliability.
4Productivity
If structured ASICs are formed to address higher volume markets, then time to market is reduced, but cost limitations arise
Solution Approach 1:
The patent further reduces cost while maintaining improved productivity by using predetermined placement information from existing PLD designs to guide ASIC structure formation. This eliminates the need for expensive custom placement and routing operations typically required for structured ASICs, as the placement is already optimized from the PLD design phase, thereby reducing both time to market and manufacturing cost.
Data Source
AI summary
A method and apparatus for a CPLD-structured ASIC. Circuit blocks associated with a programmed portion of a CPLD are configured to preserve timing associated with instantiation of a circuit design in the programmed portion of the CPLD. The circuit blocks have predetermined placement information obtained from the CPLD, and the placement information is used to locate CPLD-structured ASIC cells associated with the circuit blocks.