Common Path Pessimism Reduction in Timing Analysis
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Solution Overview
Problem
Current electronic design automation (EDA) systems face inefficiencies in timing sign-off verification and correction, leading to repetitive iterations, false-positive violations, and increased costs due to common path pessimism in timing analysis, which results in over-fixing and resource-intensive processes.
Innovation Solution
A method and system that minimize common path pessimism by generating a timing model for circuit designs with a clock root and paired clocked devices, using lineage tags to identify shared path portions and adjust timing delay parameters, thereby reducing unwarranted physical corrections and iterations between signoff and physical implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional timing analysis is used without common path pessimism removal, then timing violations are detected conservatively, but false-positive violations occur and require over-fixing
Solution Approach 1:
The patent segments the clock path into distinct portions: common path segments shared by multiple launch/capture pairs and unique path segments. By identifying and separating the common path portion, the system can apply pessimism removal only where appropriate, avoiding false-positive violations while maintaining reliability in timing analysis.
Solution Approach 2:
The patent performs preliminary identification and tagging of common path portions before conducting the full timing analysis. Lineage tags are generated in advance to mark interconnection points that belong to common paths, enabling the timing analysis tool to pre-calculate and apply pessimism removal factors, thereby reducing false-positive violations before they propagate through the design.
2Reliability
If repeated iterations between timing signoff and physical implementation are performed, then timing violations are thoroughly checked, but turn around time increases
Solution Approach 1:
The patent implements a feedback mechanism where the timing analysis results, including identified common path portions and calculated pessimism removal factors, are fed back to guide the physical implementation optimization. This feedback loop provides accurate timing information that prevents false-positive violations from triggering unnecessary design iterations, thereby reducing turn around time while maintaining thorough violation detection.
Solution Approach 2:
The patent changes the timing delay parameters by applying pessimism removal adjustments based on common path identification. By modifying the delay parameters to reflect actual common path behavior rather than conservative worst-case assumptions, the system achieves more accurate timing analysis in fewer iterations, reducing the time required for signoff verification.
3Reliability
If conservative timing analysis is used to ensure all violations are caught, then reliability is improved, but resource requirements for processing and memory increase
Solution Approach 1:
The patent extracts and removes the common path portion from the timing analysis calculation by identifying it through lineage tags. By taking out the common path segment and applying pessimism removal, the system avoids redundant conservative analysis of shared path portions, thereby reducing processing and memory resource requirements while maintaining thorough detection of actual timing violations.
Data Source
AI summary
A system and method are provided for common path pessimism removal or reduction (CPPR) in a timing database provided to guide transformative physical optimization/correction of a circuit design for an IC product to remedy operational timing violations detected in the circuit design. Pessimism is reduced through generation of a common path pessimism removal (CPPR) tree structure of branching nodes, and operational timing characteristics of each node. The CPPR tree structure is used to avoid exponential phases propagating in an exploratory manner through the system design, as well as the resultant memory footprint thereof. Additionally, back-tracing node-by-node through the circuit design for each and every launch and capture flip flop pair end point through each possible path thereof is avoided.