Detecting Faulty Computer Hardware TRIZ Cases
- Gate Sizing Optimization Using Penalty Functions
Conjugate gradient solver determines optimal gate sizes via penalty functions, reducing computational time for large circuit designs.
- Resistive Memory Model Circuit Segmentation for Accuracy
A resistive memory model circuit generates characteristic data through segmented functional blocks.
- Unified Interface for IC Physical Verification Collaboration
A unified interface consolidates DRC and LVS results, eliminating tool-switching delays during complex circuit design sign-off.
- Failure Casting Hierarchy for Computer System Recovery
A failure casting hierarchy translates diverse computer system faults into reboot-curable categories.
- Dynamic Banding Convolution for Multi-Core Memory Bottlenecks
Segmented layout and basis data fit within limited shared memory capacity, resolving bottlenecks in large dataset convolution operations.
- Context Aware Assertion Synthesis for FSM Size Reduction
Transforms PSL and SVA assertions into nested sequence implication form to reduce finite state machine size and improve formal verification performance.
- Microcontroller Data Access Control Circuit Failure Detection
A microcontroller data access control circuit executes shared thread accesses to compare commands and addresses.
- Circuit Fault Detection via Cone of Influence Intersection
Intersection analysis identifies detectable and undetectable dangerous faults, resolving incomplete safety assessment limitations in complex logic circuits.
- Interconnect Offload Component for Debug Network Data Transmission
An interconnect offload component routes functional data via a debug network, reducing interconnect load and enabling safe mode operation.
- Failover Testing Framework for Distributed State Machines
A systematic testing framework probabilistically determines event processing order to simulate failures and recoveries across distributed state machines.
- Fault Detection Computer Device for False Data Injection Attacks
A fault detection computer device generates measurement data profiles to determine the accuracy of sensor fault indications.
- Bidirectional Data Transmission Pin Reconfiguration
A data transmission system detects connection orientation to switch clock and data pin functions for flexible signal routing.
- Storage Tester Individual Control Sequence Modules
Sequence modules offload embedded processor burden by managing individual SATA, SAS, and PCIe interfaces, reducing testing time.
- RS485 Interface Access State Detection Circuit
A detection circuit determines RS485 interface access states using polarity and timer logic.
- Logic Verification Module for Multi-FPGA Debugging
A logic verification module captures signals across multiple FPGAs using tunneling circuits to consolidate debugging visibility.
- Intelligent Terminal Hardware Fault Detection via Service Layer Load Monitoring
Service layer load monitoring triggers hardware abnormality checks in intelligent terminals without pre-installed applications.
- ESD Validation for Integrated Circuits Using Parameterized Circuit Data
A system validates electrostatic discharge behavior in integrated circuits using parameterized circuit data and specialized algorithms.
- Emulation Interface for FPGA Signal Control and Observability
An emulation interface processes signal values from a custom prototype board to provide precise timing and control information for verification modules.