Gate Sizing Optimization Using Penalty Functions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing circuit synthesis approaches are computationally expensive and produce poor quality results due to the iterative trial-and-error method for determining optimal gate sizes, especially when dealing with large circuit designs and multiple process corners and modes.
Innovation Solution
A numerical solver, such as a conjugate-gradient based solver, is used to model and optimize gate sizes by selecting a portion of the circuit design, incorporating generic logical effort values and wire resistance and capacitance values, and constraining variables within a range of available gate capacitance values to optimize gate capacitance values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If iterative trial-and-error based circuit synthesis approaches are used to determine optimal gate sizes, then timing constraints can be checked across multiple process corners and modes, but the computational time becomes too long and the quality of results deteriorates for large circuit designs
Solution Approach 1:
The patent changes the approach from discrete iterative trial-and-error to continuous numerical optimization. By formulating gate sizing as a numerical optimization problem with continuous variables and using penalty functions to incorporate timing constraints, the method achieves faster computation while maintaining reliable timing constraint satisfaction across multiple process corners and modes.
2Reliability
If iterative trial-and-error based circuit synthesis approaches are used to determine optimal gate sizes, then timing constraints can be checked across multiple process corners and modes, but the quality of results becomes poor for large circuit designs
Solution Approach 1:
The patent transforms the discrete iterative optimization into a continuous numerical optimization framework. By using penalty functions to incorporate timing constraints and solving a system of equations numerically, the method achieves both faster computation and higher quality results for large circuit designs, eliminating the trade-off between reliability and productivity.
3Ease of manufacture
If gate capacitance values are constrained to discrete library values, then manufacturability is improved, but the optimization flexibility and solution quality deteriorate
Solution Approach 1:
The patent segments the optimization process into two stages: first, continuous numerical optimization to determine optimal gate capacitance values and sizing relationships; second, mapping the continuous results to discrete library values. This segmentation allows the optimization to maintain full mathematical flexibility while ensuring manufacturability through the final discretization step.
Solution Approach 2:
The patent introduces penalty functions as intermediaries that bridge the continuous optimization domain and discrete library domain. The penalty functions incorporate timing constraints and guide the continuous optimization toward solutions that can be successfully mapped to discrete library values, maintaining both optimization flexibility and manufacturability.
Data Source
AI summary
Systems and techniques are described for optimizing a circuit design by using a numerical solver. The gates sizes are optimized by modeling a set of gate optimization problems and solving the set of gate optimization problems by using a numerical solver. The optimization can be performed iteratively, wherein in each iteration a gate optimization problem can be modeled for the portion of the circuit design based on circuit information for the portion of the circuit design. An objective function can be created, wherein the objective function includes at least one penalty function that imposes a lower and/or upper bound on at least one variable that is being optimized. In some embodiments, gradients of the objective function, which includes the penalty function, can be computed to enable the use of a conjugate-gradient-based numerical solver.