Interconnect Offload Component for Debug Network Data Transmission
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Advanced signal processing devices, such as System-on-Chip (SoC) devices, face performance limitations due to the speed of data communication between components via the interconnect component, and implementing a safe mode in case of errors or malfunctions within the interconnect component is challenging, especially in safety-critical applications.
Innovation Solution
An interconnect offload component and a memory access component are introduced to offload functional data from the interconnect component onto a debug network, reducing the load on the interconnect component and enabling a safe mode operation by using the debug network for non-coherent data transmission, thereby improving performance and ensuring system safety.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If functional data is transmitted through the interconnect component, then data communication between components is achieved, but the interconnect component becomes a performance bottleneck and reliability risk
Solution Approach 1:
The patent introduces an intermediary component (the offload component) that mediates between the interconnect component and the debug network. This intermediary receives functional data from the interconnect component and forwards it to the debug network, thereby isolating the interconnect component from direct reliability risks while maintaining data communication functionality.
Solution Approach 2:
The patent segments the data transmission path by separating functional data transmission from the interconnect component. By dividing the data flow into interconnect component data and debug network data, the system eliminates the single point of failure risk associated with relying solely on the interconnect component for all data communication.
2Device complexity
If the interconnect component is used for all data transmission, then component simplicity is maintained, but performance limitations are encountered
Solution Approach 1:
The patent applies multi-functionality by enabling the debug network to serve dual purposes: traditional debug/trace functionality and functional data transmission. This allows the system to achieve higher data communication throughput without adding a completely separate transmission infrastructure, as the debug network is repurposed to handle functional data offloading.
Solution Approach 2:
The patent introduces a new dimension to data transmission by utilizing the debug network as an additional transmission pathway. Instead of solely relying on the interconnect component's spatial transmission path, the system adds a temporal/logical dimension by multiplexing functional data onto the debug network, thereby increasing overall communication capacity.
3Productivity
If functional data is offloaded to the debug network, then interconnect component load is reduced, but the debug network must handle non-coherent data transmission
Solution Approach 1:
The patent extracts non-coherent data transmission functionality from the interconnect component and places it in the debug network. By taking out the coherence requirements from the functional data path and placing them in the debug network's error detection/correction mechanisms, the system enables high-speed offloading while managing the added complexity through targeted error handling rather than full coherence maintenance.
Data Source
AI summary
An interconnect offload component arranged to operate in an offloading mode, and a memory access component for enabling access to a memory element for functional data transmitted over a debug network of a signal processing device.In the offloading mode the interconnect offload component is arranged to receive functional data from an interconnect client component for communication to a destination component, and forward at least a part of the received functional data to a debug network for communication to the destination component via the debug network.The memory access component is arranged to receive a debug format message transmitted over the debug network, extract functional data from the received debug format message, said functional data originating from an interconnect client component for communication to a memory element, and perform a direct memory access to the memory element comprising the extracted functional data.