Storage Tester Individual Control Sequence Modules
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Solution Overview
Problem
Existing storage testers face inefficiencies in testing multiple SATA/SAS/PCIe interfaces due to the high processing burden on a single embedded processor, leading to increased testing time when different control instructions are transmitted simultaneously.
Innovation Solution
A storage tester design utilizing multiple sequence control modules to individually control multiple SATA/SAS/PCIe interfaces using a single embedded processor, reducing overall testing time by distributing control commands efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single embedded processor is used to control multiple SATA/SAS/PCIe interface units, then the device complexity is reduced, but the testing time increases due to the processing burden on the embedded processor
Solution Approach 1:
The patent divides the control function into two parts: the embedded processor handles high-level test logic and coordination, while sequence control modules (implemented as FPGA or ASIC) handle low-level interface control for multiple SATA/SAS/PCIe interfaces. This segmentation allows parallel processing of multiple storage devices without overloading the embedded processor, thereby reducing testing time while maintaining reasonable device complexity.
Solution Approach 2:
The sequence control modules act as intermediaries between the embedded processor and the SATA/SAS/PCIe interface units. These intermediaries offload the burden of real-time interface control from the embedded processor, enabling simultaneous control of multiple interfaces without increasing the complexity of the embedded processor itself.
2Loss of time
If multiple embedded processors are used to control multiple SATA/SAS/PCIe interface units simultaneously, then the testing time is reduced, but the device complexity and manufacturing cost increase
Solution Approach 1:
Instead of using multiple embedded processors, the patent segments the control function by introducing sequence control modules as dedicated hardware assistants. Each sequence control module can independently manage one or more SATA/SAS/PCIe interfaces, enabling parallel processing that reduces testing time without requiring multiple full-featured embedded processors.
Solution Approach 2:
The sequence control modules are implemented using reusable hardware templates (FPGA or ASIC designs) that can be instantiated multiple times. This copying approach allows the system to have multiple identical control units for parallel interface management, reducing testing time while avoiding the complexity of designing and managing multiple different embedded processors.
3Device complexity
If different control instructions are transmitted to multiple SATA/SAS/PCIe interface units at different points in time using a single embedded processor, then the device complexity is maintained, but the productivity decreases due to increased testing time
Solution Approach 1:
The patent segments the control architecture so that the embedded processor focuses on test sequence management while sequence control modules handle real-time interface control. This segmentation enables simultaneous transmission of control instructions to multiple SATA/SAS/PCIe interface units, significantly improving productivity without requiring the embedded processor to handle all low-level control tasks.
Solution Approach 2:
The sequence control modules enable continuous and simultaneous control of multiple SATA/SAS/PCIe interfaces without the sequential bottlenecks of a single embedded processor. This continuity allows the system to maintain high productivity by eliminating idle time between control operations on different interfaces.
Data Source
AI summary
Disclosed is a storage tester capable of individual control for a plurality of storages, which comprises a host terminal for receiving user's control signal for storage test; a communication interface unit transmitting data among the host terminal, an embedded processor and a data engine unit; a data engine unit for generating pattern data and command data and reading the data from the storage; a sequence control module for controlling respectively a plurality of SATA/SAS/PCIe interface units; and SATA/SAS/PCIe interface unit for connecting to the storage through one among SATA, SAS, PCIe interface according to the signal for interface selection generated from the embedded processor and controlling a plurality of storages according to control of the sequence control module by the embedded processor in order to test respectively connected storage.