Logic Verification Module for Multi-FPGA Debugging
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Solution Overview
Problem
Debugging complex electronic circuits that span multiple Field Programmable Gate Arrays (FPGAs) is challenging due to limited pin resources, which restricts the observability and debugging capabilities, making it difficult to identify issues that cross FPGA boundaries.
Innovation Solution
A system and method that uses a reconfigurable platform with a logic verification module and data value tunneling circuits to enable logic value capture and analysis across multiple FPGAs, allowing full visibility of partitions and efficient signal transfer between FPGAs, utilizing techniques like SERDES, LVDS, and multiplexors to overcome pin limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single FPGA is used for prototyping, then device complexity is reduced, but observability and debugging capability deteriorate due to limited pin resources
Solution Approach 1:
The system divides the debugging functionality into separate modules: a logic verification module embedded in one FPGA and user logic partitions distributed across multiple FPGAs. This segmentation allows each FPGA to have dedicated observation capabilities without consuming excessive pin resources, as the verification module independently manages signal capture and analysis across the partitioned system.
Solution Approach 2:
The logic verification module acts as an intermediary between the user logic partitions and the host computer. It captures logic values from multiple FPGAs, processes the data, and communicates results to the host, thereby enabling comprehensive observability without requiring direct pin connections from every user logic signal to external debug equipment.
2Difficulty of detecting and measuring
If multiple FPGAs are used to debug complex circuits, then signal observability improves, but device complexity and routing resources increase
Solution Approach 1:
The logic verification module is designed with multi-functionality, serving as both a debugging instrument and a signal capture device across multiple FPGAs. By embedding this universal module in one FPGA, the system achieves comprehensive observability of partitioned logic without requiring separate debugging equipment for each FPGA, thereby reducing overall device complexity.
Solution Approach 2:
The system merges the debugging and verification functionality into a single logic verification module that operates across multiple FPGAs. This consolidation eliminates the need for separate logic analyzers in each FPGA, reducing routing resources and logic element consumption while maintaining full observability of the partitioned design.
3Difficulty of detecting and measuring
If logic analyzer resources are increased in a single FPGA, then debugging capability improves, but available logic elements and routing channels for user logic decrease
Solution Approach 1:
The system extracts the logic analyzer functionality from the user logic partitions and places it in a dedicated logic verification module. This extraction allows the verification module to have extensive logic elements and routing channels for debugging purposes without consuming resources from the user logic, as the two functions are physically separated in different FPGAs or partitioned regions.
Data Source
AI summary
A apparatus and a system and method to operate the above provide a reconfigurable platform for emulating and debugging a user design which exceeds the capacity of a single field programmable logic device (FPGA). The method and system facilitates design and emulation of a system-on-a-chip type user design. The netlist of a user design may be included with logic value tunneling circuits in an emulation using a platform including a number of field programmable devices. A verification module apparatus provides a hyper prototype for debugging an electronic design that exceeds the capacity of a single FPGA. A verification module provides access to a plurality of attached FPGAs by means of Logic Value Tunneling Transmitters and Receivers which deliver many signals over few pins.