Unified Interface for IC Physical Verification Collaboration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The complexity of modern integrated circuit designs makes physical verification of entire circuits challenging, as errors can arise from interactions between component cells or blocks, requiring laborious and time-consuming collaboration among design teams using conventional methods.
Innovation Solution
A collaborative environment is created for physical verification processes, allowing multiple designers to concurrently access, edit, and annotate integrated circuit designs through a unified interface, with features like a unified results database, incremental design rule check, and communication tools, facilitating team collaboration and error resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple designers collaborate on physical verification using conventional methods, then error resolution can be achieved, but the process becomes laborious and time-consuming
Solution Approach 1:
The patent merges multiple designers' verification activities into a single unified graphical user interface that displays consolidated error results from design rule checks, layout versus schematic comparisons, and other physical verification processes. This consolidation allows simultaneous viewing and collaborative resolution of all errors in one interface, eliminating the need to switch between multiple tools and significantly reducing collaboration time while maintaining comprehensive error resolution capability
Solution Approach 2:
The patent introduces a unified graphical user interface as an intermediary layer between multiple verification tools and the design team. This intermediary consolidates error results from various sources (DRC, LVS, etc.) into a single view, enabling efficient collaboration without requiring designers to directly interact with multiple complex tools simultaneously, thus reducing time loss while preserving error resolution effectiveness
2Reliability
If physical verification of entire circuits is performed to detect interaction errors, then design reliability is improved, but the verification complexity increases
Solution Approach 1:
The patent segments the complex physical verification process into distinct categories (design rule check errors, layout versus schematic comparison errors, and other verification errors), each displayed as separate filterable groups within the unified interface. This segmentation allows the verification system to comprehensively check entire circuits for interaction errors while organizing results in a manageable, less complex format that reduces the perceived verification complexity for users
Solution Approach 2:
The patent creates a universal graphical user interface that handles multiple types of physical verification errors (DRC, LVS, and other verification errors) through a single consolidated display and interaction mechanism. This multi-functional interface reduces verification complexity by providing a unified approach to managing diverse error types, while still enabling comprehensive reliability checking of entire circuits
Data Source
AI summary
A collaborative environment for performing physical verification processes on integrated circuit designs. Multiple physical verification results may be stored in a “unified” results database/directory (e.g., unified at least from a user's perspective), where results from various verification processes, such as Design-Rule-Check (DRC) processes, Layout-Versus-Schematic comparison (LVS) processes, Design-For-Manufacturing (DFM) processes Optical Proximity Correction (OPC) processes, and Optical Rule Check (ORC) processes are accessible from the same style of user interface, which may be a graphical user interface. The basic abilities for design team-based interactions can be equally available to each process involved in the physical verification of an integrated circuit design.